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Searched refs:CLK_SRC_TOP0_VAL (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock_init_exynos4.c48 writel(CLK_SRC_TOP0_VAL, &clk->src_top0); in system_clock_init()
Dexynos5_setup.h535 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ macro
783 #define CLK_SRC_TOP0_VAL 0x12221222 macro
Dexynos4_setup.h126 #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \ macro
Dclock_init_exynos5.c690 writel(CLK_SRC_TOP0_VAL, &clk->src_top0); in exynos5250_system_clock_init()
914 writel(CLK_SRC_TOP0_VAL, &clk->src_top0); in exynos5420_system_clock_init()
/external/u-boot/board/samsung/trats/
Dtrats.c318 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); in board_clock_init()
Dsetup.h93 #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \ macro