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Searched refs:CLK_SRC_TOP1_VAL (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock_init_exynos4.c49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
Dexynos5_setup.h551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
Dexynos4_setup.h138 #define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL) macro
Dclock_init_exynos5.c691 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in exynos5250_system_clock_init()
915 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in exynos5420_system_clock_init()