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1 /*
2  * This header provides constants clk index STMicroelectronics
3  * STiH407 SoC.
4  */
5 #ifndef _DT_BINDINGS_CLK_STIH407
6 #define _DT_BINDINGS_CLK_STIH407
7 
8 /* CLOCKGEN A0 */
9 #define CLK_IC_LMI0		0
10 #define CLK_IC_LMI1		1
11 
12 /* CLOCKGEN C0 */
13 #define CLK_ICN_GPU		0
14 #define CLK_FDMA		1
15 #define CLK_NAND		2
16 #define CLK_HVA			3
17 #define CLK_PROC_STFE		4
18 #define CLK_PROC_TP		5
19 #define CLK_RX_ICN_DMU		6
20 #define CLK_RX_ICN_DISP_0	6
21 #define CLK_RX_ICN_DISP_1	6
22 #define CLK_RX_ICN_HVA		7
23 #define CLK_RX_ICN_TS		7
24 #define CLK_ICN_CPU		8
25 #define CLK_TX_ICN_DMU		9
26 #define CLK_TX_ICN_HVA		9
27 #define CLK_TX_ICN_TS		9
28 #define CLK_ICN_COMPO		9
29 #define CLK_MMC_0		10
30 #define CLK_MMC_1		11
31 #define CLK_JPEGDEC		12
32 #define CLK_ICN_REG		13
33 #define CLK_TRACE_A9		13
34 #define CLK_PTI_STM		13
35 #define CLK_EXT2F_A9		13
36 #define CLK_IC_BDISP_0		14
37 #define CLK_IC_BDISP_1		15
38 #define CLK_PP_DMU		16
39 #define CLK_VID_DMU		17
40 #define CLK_DSS_LPC		18
41 #define CLK_ST231_AUD_0		19
42 #define CLK_ST231_GP_0		19
43 #define CLK_ST231_GP_1		20
44 #define CLK_ST231_DMU		21
45 #define CLK_ICN_LMI		22
46 #define CLK_TX_ICN_DISP_0	23
47 #define CLK_TX_ICN_DISP_1	23
48 #define CLK_ICN_SBC		24
49 #define CLK_STFE_FRC2		25
50 #define CLK_ETH_PHY		26
51 #define CLK_ETH_REF_PHYCLK	27
52 #define CLK_FLASH_PROMIP	28
53 #define CLK_MAIN_DISP		29
54 #define CLK_AUX_DISP		30
55 #define CLK_COMPO_DVP		31
56 
57 /* CLOCKGEN D0 */
58 #define CLK_PCM_0		0
59 #define CLK_PCM_1		1
60 #define CLK_PCM_2		2
61 #define CLK_SPDIFF		3
62 
63 /* CLOCKGEN D2 */
64 #define CLK_PIX_MAIN_DISP	0
65 #define CLK_PIX_PIP		1
66 #define CLK_PIX_GDP1		2
67 #define CLK_PIX_GDP2		3
68 #define CLK_PIX_GDP3		4
69 #define CLK_PIX_GDP4		5
70 #define CLK_PIX_AUX_DISP	6
71 #define CLK_DENC		7
72 #define CLK_PIX_HDDAC		8
73 #define CLK_HDDAC		9
74 #define CLK_SDDAC		10
75 #define CLK_PIX_DVO		11
76 #define CLK_DVO			12
77 #define CLK_PIX_HDMI		13
78 #define CLK_TMDS_HDMI		14
79 #define CLK_REF_HDMIPHY		15
80 
81 /* CLOCKGEN D3 */
82 #define CLK_STFE_FRC1		0
83 #define CLK_TSOUT_0		1
84 #define CLK_TSOUT_1		2
85 #define CLK_MCHI		3
86 #define CLK_VSENS_COMPO		4
87 #define CLK_FRC1_REMOTE		5
88 #define CLK_LPC_0		6
89 #define CLK_LPC_1		7
90 #endif
91