| /external/u-boot/arch/arm/mach-tegra/tegra114/ |
| D | clock.c | 664 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
665 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
674 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
679 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
684 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
701 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
742 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /external/u-boot/arch/arm/mach-tegra/ |
| D | clock.c | 689 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); in clock_init()
701 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); in clock_init()
766 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); in tegra30_set_up_pllp()
771 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in tegra30_set_up_pllp()
776 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in tegra30_set_up_pllp()
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| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| D | clock.c | 844 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
845 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
854 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
859 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
864 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
878 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
881 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
882 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
1168 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /external/u-boot/arch/arm/mach-tegra/tegra210/ |
| D | clock.c | 984 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
989 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
994 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
998 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); in clock_early_init()
1002 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); in clock_early_init()
1015 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, in clock_early_init()
1023 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], in clock_early_init()
1268 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /external/u-boot/arch/arm/mach-tegra/tegra20/ |
| D | clock.c | 589 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
594 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
599 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
759 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /external/u-boot/arch/arm/include/asm/arch-tegra20/ |
| D | clock-tables.h | 15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /external/u-boot/drivers/video/ |
| D | tegra.c | 133 rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); in update_display_mode()
280 clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, in tegra_display_probe()
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| /external/u-boot/arch/arm/include/asm/arch-tegra114/ |
| D | clock-tables.h | 14 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /external/u-boot/arch/arm/include/asm/arch-tegra30/ |
| D | clock-tables.h | 14 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /external/u-boot/arch/arm/include/asm/arch-tegra124/ |
| D | clock-tables.h | 15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /external/u-boot/arch/arm/include/asm/arch-tegra210/ |
| D | clock-tables.h | 15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /external/u-boot/arch/arm/mach-tegra/tegra30/ |
| D | clock.c | 806 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|