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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010
4  * Texas Instruments, <www.ti.com>
5  *
6  *	Aneesh V <aneesh@ti.com>
7  *	Sricharan R <r.sricharan@ti.com>
8  */
9 #ifndef _CLOCKS_OMAP5_H_
10 #define _CLOCKS_OMAP5_H_
11 #include <common.h>
12 #include <asm/omap_common.h>
13 
14 /*
15  * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
16  * loop, allow for a minimum of 2 ms wait (in reality the wait will be
17  * much more than that)
18  */
19 #define LDELAY		1000000
20 
21 /* CM_DLL_CTRL */
22 #define CM_DLL_CTRL_OVERRIDE_SHIFT		0
23 #define CM_DLL_CTRL_OVERRIDE_MASK		(1 << 0)
24 #define CM_DLL_CTRL_NO_OVERRIDE			0
25 
26 /* CM_CLKMODE_DPLL */
27 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
28 #define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
29 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
30 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
31 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
32 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
33 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
34 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
35 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
36 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
37 #define CM_CLKMODE_DPLL_EN_SHIFT		0
38 #define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
39 
40 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
41 #define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
42 
43 #define DPLL_EN_STOP			1
44 #define DPLL_EN_MN_BYPASS		4
45 #define DPLL_EN_LOW_POWER_BYPASS	5
46 #define DPLL_EN_FAST_RELOCK_BYPASS	6
47 #define DPLL_EN_LOCK			7
48 
49 /* CM_IDLEST_DPLL fields */
50 #define ST_DPLL_CLK_MASK		1
51 
52 /* SGX */
53 #define CLKSEL_GPU_HYD_GCLK_MASK		(1 << 25)
54 #define CLKSEL_GPU_CORE_GCLK_MASK		(1 << 24)
55 
56 /* CM_CLKSEL_DPLL */
57 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
58 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
59 #define CM_CLKSEL_DPLL_M_SHIFT			8
60 #define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
61 #define CM_CLKSEL_DPLL_N_SHIFT			0
62 #define CM_CLKSEL_DPLL_N_MASK			0x7F
63 #define CM_CLKSEL_DCC_EN_SHIFT			22
64 #define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
65 
66 /* CM_SYS_CLKSEL */
67 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
68 
69 /* CM_CLKSEL_CORE */
70 #define CLKSEL_CORE_SHIFT	0
71 #define CLKSEL_L3_SHIFT		4
72 #define CLKSEL_L4_SHIFT		8
73 
74 #define CLKSEL_CORE_X2_DIV_1	0
75 #define CLKSEL_L3_CORE_DIV_2	1
76 #define CLKSEL_L4_L3_DIV_2	1
77 
78 /* CM_ABE_PLL_REF_CLKSEL */
79 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
80 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
81 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
82 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
83 
84 /* CM_CLKSEL_ABE_PLL_SYS */
85 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT	0
86 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK	1
87 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1		0
88 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2		1
89 
90 /* CM_BYPCLK_DPLL_IVA */
91 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
92 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
93 
94 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
95 
96 /* CM_SHADOW_FREQ_CONFIG1 */
97 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
98 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
99 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
100 
101 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
102 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
103 
104 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
105 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
106 
107 /*CM_<clock_domain>__CLKCTRL */
108 #define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
109 #define CD_CLKCTRL_CLKTRCTRL_MASK		3
110 
111 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
112 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
113 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
114 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
115 
116 
117 /* CM_<clock_domain>_<module>_CLKCTRL */
118 #define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
119 #define MODULE_CLKCTRL_MODULEMODE_MASK		3
120 #define MODULE_CLKCTRL_IDLEST_SHIFT		16
121 #define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
122 
123 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
124 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
125 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
126 
127 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
128 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
129 #define MODULE_CLKCTRL_IDLEST_IDLE		2
130 #define MODULE_CLKCTRL_IDLEST_DISABLED		3
131 
132 /* CM_L4PER_GPIO4_CLKCTRL */
133 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
134 
135 /* CM_L3INIT_HSMMCn_CLKCTRL */
136 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
137 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(3 << 25)
138 
139 /* CM_L3INIT_SATA_CLKCTRL */
140 #define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
141 
142 /* CM_WKUP_GPTIMER1_CLKCTRL */
143 #define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
144 
145 /* CM_CAM_ISS_CLKCTRL */
146 #define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
147 
148 /* CM_DSS_DSS_CLKCTRL */
149 #define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
150 
151 /* CM_L3INIT_USBPHY_CLKCTRL */
152 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
153 
154 /* CM_L3INIT_USB_HOST_HS_CLKCTRL */
155 #define OPTFCLKEN_FUNC48M_CLK			(1 << 15)
156 #define OPTFCLKEN_HSIC480M_P2_CLK		(1 << 14)
157 #define OPTFCLKEN_HSIC480M_P1_CLK		(1 << 13)
158 #define OPTFCLKEN_HSIC60M_P2_CLK		(1 << 12)
159 #define OPTFCLKEN_HSIC60M_P1_CLK		(1 << 11)
160 #define OPTFCLKEN_UTMI_P3_CLK			(1 << 10)
161 #define OPTFCLKEN_UTMI_P2_CLK			(1 << 9)
162 #define OPTFCLKEN_UTMI_P1_CLK			(1 << 8)
163 #define OPTFCLKEN_HSIC480M_P3_CLK		(1 << 7)
164 #define OPTFCLKEN_HSIC60M_P3_CLK		(1 << 6)
165 
166 /* CM_L3INIT_USB_TLL_HS_CLKCTRL */
167 #define OPTFCLKEN_USB_CH0_CLK_ENABLE	(1 << 8)
168 #define OPTFCLKEN_USB_CH1_CLK_ENABLE	(1 << 9)
169 #define OPTFCLKEN_USB_CH2_CLK_ENABLE	(1 << 10)
170 
171 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */
172 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
173 
174 /* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
175 #define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK	(1 << 8)
176 
177 /* CM_L3INIT_USB_OTG_SS_CLKCTRL */
178 #define OTG_SS_CLKCTRL_MODULEMODE_HW	(1 << 0)
179 #define OPTFCLKEN_REFCLK960M			(1 << 8)
180 
181 /* CM_L3INIT_OCP2SCP1_CLKCTRL */
182 #define OCP2SCP1_CLKCTRL_MODULEMODE_HW	(1 << 0)
183 
184 /* CM_MPU_MPU_CLKCTRL */
185 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
186 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)
187 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	26
188 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 26)
189 
190 /* CM_WKUPAON_SCRM_CLKCTRL */
191 #define OPTFCLKEN_SCRM_PER_SHIFT		9
192 #define OPTFCLKEN_SCRM_PER_MASK			(1 << 9)
193 #define OPTFCLKEN_SCRM_CORE_SHIFT		8
194 #define OPTFCLKEN_SCRM_CORE_MASK		(1 << 8)
195 
196 /* CM_COREAON_IO_SRCOMP_CLKCTRL */
197 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT		8
198 #define OPTFCLKEN_SRCOMP_FCLK_MASK		(1 << 8)
199 
200 /* PRM_RSTTIME */
201 #define RSTTIME1_SHIFT				0
202 #define RSTTIME1_MASK				(0x3ff << 0)
203 
204 /* Clock frequencies */
205 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
206 
207 /* PRM_VC_VAL_BYPASS */
208 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
209 
210 /* CTRL_CORE_SRCOMP_NORTH_SIDE */
211 #define USB2PHY_DISCHGDET	(1 << 29)
212 #define USB2PHY_AUTORESUME_EN (1 << 30)
213 
214 /* SMPS */
215 #define SMPS_I2C_SLAVE_ADDR	0x12
216 #define SMPS_REG_ADDR_12_MPU	0x23
217 #define SMPS_REG_ADDR_45_IVA	0x2B
218 #define SMPS_REG_ADDR_8_CORE	0x37
219 
220 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
221 /* ES1.0 settings */
222 #define VDD_MPU		1040
223 #define VDD_MM		1040
224 #define VDD_CORE	1040
225 
226 #define VDD_MPU_LOW	890
227 #define VDD_MM_LOW	890
228 #define VDD_CORE_LOW	890
229 
230 /* ES2.0 settings */
231 #define VDD_MPU_ES2	1060
232 #define VDD_MM_ES2	1025
233 #define VDD_CORE_ES2	1040
234 
235 #define VDD_MPU_ES2_HIGH 1250
236 #define VDD_MM_ES2_OD  1120
237 
238 /* Efuse register offsets for OMAP5 platform */
239 #define OMAP5_ES2_EFUSE_BASE	0x4A002000
240 #define OMAP5_ES2_PROD_REGBITS	16
241 
242 /* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */
243 #define OMAP5_ES2_PROD_CORE_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1D8)
244 
245 /* CONTROL_STD_FUSE_OPP_VDD_MM_4 */
246 #define OMAP5_ES2_PROD_MM_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1A4)
247 /* CONTROL_STD_FUSE_OPP_VDD_MM_5 */
248 #define OMAP5_ES2_PROD_MM_OPOD_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1A8)
249 /* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */
250 #define OMAP5_ES2_PROD_MPU_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1C4)
251 /* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */
252 #define OMAP5_ES2_PROD_MPU_OPHI_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1C8)
253 
254 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
255 #define VDD_MPU_DRA7_NOM	1150
256 #define VDD_CORE_DRA7_NOM	1150
257 #define VDD_EVE_DRA7_NOM	1060
258 #define VDD_GPU_DRA7_NOM	1060
259 #define VDD_IVA_DRA7_NOM	1060
260 
261 /* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
262 #define VDD_EVE_DRA7_OD		1150
263 #define VDD_GPU_DRA7_OD		1150
264 #define VDD_IVA_DRA7_OD		1150
265 
266 /* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
267 #define VDD_EVE_DRA7_HIGH	1250
268 #define VDD_GPU_DRA7_HIGH	1250
269 #define VDD_IVA_DRA7_HIGH	1250
270 
271 /* Efuse register offsets for DRA7xx platform */
272 #define DRA752_EFUSE_BASE	0x4A002000
273 #define DRA752_EFUSE_REGBITS	16
274 /* STD_FUSE_OPP_VMIN_IVA_2 */
275 #define STD_FUSE_OPP_VMIN_IVA_NOM	(DRA752_EFUSE_BASE + 0x05CC)
276 /* STD_FUSE_OPP_VMIN_IVA_3 */
277 #define STD_FUSE_OPP_VMIN_IVA_OD	(DRA752_EFUSE_BASE + 0x05D0)
278 /* STD_FUSE_OPP_VMIN_IVA_4 */
279 #define STD_FUSE_OPP_VMIN_IVA_HIGH	(DRA752_EFUSE_BASE + 0x05D4)
280 /* STD_FUSE_OPP_VMIN_DSPEVE_2 */
281 #define STD_FUSE_OPP_VMIN_DSPEVE_NOM	(DRA752_EFUSE_BASE + 0x05E0)
282 /* STD_FUSE_OPP_VMIN_DSPEVE_3 */
283 #define STD_FUSE_OPP_VMIN_DSPEVE_OD	(DRA752_EFUSE_BASE + 0x05E4)
284 /* STD_FUSE_OPP_VMIN_DSPEVE_4 */
285 #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH	(DRA752_EFUSE_BASE + 0x05E8)
286 /* STD_FUSE_OPP_VMIN_CORE_2 */
287 #define STD_FUSE_OPP_VMIN_CORE_NOM	(DRA752_EFUSE_BASE + 0x05F4)
288 /* STD_FUSE_OPP_VMIN_GPU_2 */
289 #define STD_FUSE_OPP_VMIN_GPU_NOM	(DRA752_EFUSE_BASE + 0x1B08)
290 /* STD_FUSE_OPP_VMIN_GPU_3 */
291 #define STD_FUSE_OPP_VMIN_GPU_OD	(DRA752_EFUSE_BASE + 0x1B0C)
292 /* STD_FUSE_OPP_VMIN_GPU_4 */
293 #define STD_FUSE_OPP_VMIN_GPU_HIGH	(DRA752_EFUSE_BASE + 0x1B10)
294 /* STD_FUSE_OPP_VMIN_MPU_2 */
295 #define STD_FUSE_OPP_VMIN_MPU_NOM	(DRA752_EFUSE_BASE + 0x1B20)
296 /* STD_FUSE_OPP_VMIN_MPU_3 */
297 #define STD_FUSE_OPP_VMIN_MPU_OD	(DRA752_EFUSE_BASE + 0x1B24)
298 /* STD_FUSE_OPP_VMIN_MPU_4 */
299 #define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
300 
301 #if defined(CONFIG_DRA7_MPU_OPP_HIGH)
302 #define DRA7_MPU_OPP	OPP_HIGH
303 #elif defined(CONFIG_DRA7_MPU_OPP_OD)
304 #define DRA7_MPU_OPP	OPP_OD
305 #else /* OPP_NOM default */
306 #define DRA7_MPU_OPP	OPP_NOM
307 #endif
308 
309 /* OPP_NOM only available option for CORE */
310 #define DRA7_CORE_OPP	OPP_NOM
311 
312 #if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
313 #define DRA7_DSPEVE_OPP	OPP_HIGH
314 #elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
315 #define DRA7_DSPEVE_OPP	OPP_OD
316 #else /* OPP_NOM default */
317 #define DRA7_DSPEVE_OPP	OPP_NOM
318 #endif
319 
320 #if defined(CONFIG_DRA7_IVA_OPP_HIGH)
321 #define DRA7_IVA_OPP	OPP_HIGH
322 #elif defined(CONFIG_DRA7_IVA_OPP_OD)
323 #define DRA7_IVA_OPP	OPP_OD
324 #else /* OPP_NOM default */
325 #define DRA7_IVA_OPP	OPP_NOM
326 #endif
327 
328 #if defined(CONFIG_DRA7_GPU_OPP_HIGH)
329 #define DRA7_GPU_OPP	OPP_HIGH
330 #elif defined(CONFIG_DRA7_GPU_OPP_OD)
331 #define DRA7_GPU_OPP	OPP_OD
332 #else /* OPP_NOM default */
333 #define DRA7_GPU_OPP	OPP_NOM
334 #endif
335 
336 /* Standard offset is 0.5v expressed in uv */
337 #define PALMAS_SMPS_BASE_VOLT_UV 500000
338 
339 /* Offset is 0.73V for LP873x */
340 #define LP873X_BUCK_BASE_VOLT_UV		730000
341 
342 /* Offset is 0.73V for LP87565 */
343 #define LP87565_BUCK_BASE_VOLT_UV		730000
344 
345 /* TPS659038 */
346 #define TPS659038_I2C_SLAVE_ADDR		0x58
347 #define TPS659038_REG_ADDR_SMPS12		0x23
348 #define TPS659038_REG_ADDR_SMPS45		0x2B
349 #define TPS659038_REG_ADDR_SMPS6		0x2F
350 #define TPS659038_REG_ADDR_SMPS7		0x33
351 #define TPS659038_REG_ADDR_SMPS8		0x37
352 
353 /* TPS65917 */
354 #define TPS65917_I2C_SLAVE_ADDR		0x58
355 #define TPS65917_REG_ADDR_SMPS1		0x23
356 #define TPS65917_REG_ADDR_SMPS2		0x27
357 #define TPS65917_REG_ADDR_SMPS3		0x2F
358 #define TPS65917_REG_ADDR_SMPS4		0x33
359 
360 /* LP873X */
361 #define LP873X_I2C_SLAVE_ADDR		0x60
362 #define LP873X_REG_ADDR_BUCK0		0x6
363 #define LP873X_REG_ADDR_BUCK1		0x7
364 #define LP873X_REG_ADDR_LDO1		0xA
365 
366 /* LP87565 */
367 #define LP87565_I2C_SLAVE_ADDR		0x61
368 #define LP87565_REG_ADDR_BUCK01		0xA
369 #define LP87565_REG_ADDR_BUCK23		0xE
370 
371 /* TPS */
372 #define TPS62361_I2C_SLAVE_ADDR		0x60
373 #define TPS62361_REG_ADDR_SET0		0x0
374 #define TPS62361_REG_ADDR_SET1		0x1
375 #define TPS62361_REG_ADDR_SET2		0x2
376 #define TPS62361_REG_ADDR_SET3		0x3
377 #define TPS62361_REG_ADDR_CTRL		0x4
378 #define TPS62361_REG_ADDR_TEMP		0x5
379 #define TPS62361_REG_ADDR_RMP_CTRL	0x6
380 #define TPS62361_REG_ADDR_CHIP_ID	0x8
381 #define TPS62361_REG_ADDR_CHIP_ID_2	0x9
382 
383 #define TPS62361_BASE_VOLT_MV	500
384 #define TPS62361_VSEL0_GPIO	7
385 
386 /* Defines for DPLL setup */
387 #define DPLL_LOCKED_FREQ_TOLERANCE_0		0
388 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
389 #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
390 
391 #define DPLL_NO_LOCK	0
392 #define DPLL_LOCK	1
393 
394 #if defined(CONFIG_DRA7XX)
395 #define V_OSCK			20000000	/* Clock output from T2 */
396 #else
397 #define V_OSCK			19200000	/* Clock output from T2 */
398 #endif
399 
400 #define V_SCLK	V_OSCK
401 
402 /* CKO buffer control */
403 #define CKOBUFFER_CLK_ENABLE_MASK	(1 << 28)
404 
405 /* AUXCLKx reg fields */
406 #define AUXCLK_ENABLE_MASK		(1 << 8)
407 #define AUXCLK_SRCSELECT_SHIFT		1
408 #define AUXCLK_SRCSELECT_MASK		(3 << 1)
409 #define AUXCLK_CLKDIV_SHIFT		16
410 #define AUXCLK_CLKDIV_MASK		(0xF << 16)
411 
412 #define AUXCLK_SRCSELECT_SYS_CLK	0
413 #define AUXCLK_SRCSELECT_CORE_DPLL	1
414 #define AUXCLK_SRCSELECT_PER_DPLL	2
415 #define AUXCLK_SRCSELECT_ALTERNATE	3
416 
417 #endif /* _CLOCKS_OMAP5_H_ */
418