| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_tex.c | 403 #define COMBINE(x, y) x, y macro
407 COMBINE(0, 0),
417 COMBINE(0, 0),
418 COMBINE(1, 0),
427 COMBINE(0, 0),
428 COMBINE(1, 0),
429 COMBINE(0, 1),
430 COMBINE(1, 1),
437 COMBINE(0, 0),
438 COMBINE(1, 0),
[all …]
|
| /external/grpc-grpc/test/core/bad_client/ |
| D | bad_client.h | 69 #define COMBINE(X, Y) COMBINE1(X, Y) macro
73 grpc_bad_client_arg COMBINE(bca, __LINE__) = {client_validator, nullptr, \
75 grpc_run_bad_client_test(server_validator, &COMBINE(bca, __LINE__), 1, flags)
|
| /external/v8/src/ |
| D | register-configuration.cc | 110 kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE, in ArchDefaultRegisterConfiguration()
134 kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE, in ArchDefaultPoisoningRegisterConfiguration()
182 kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE, in ArchPreserveRootIA32RegisterConfiguration()
233 kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE, in RestrictedRegisterConfiguration()
333 if (fp_aliasing_kind_ == COMBINE) { in RegisterConfiguration()
389 DCHECK(fp_aliasing_kind_ == COMBINE); in GetAliases()
415 DCHECK(fp_aliasing_kind_ == COMBINE); in AreAliases()
|
| D | register-configuration.h | 24 COMBINE enumerator
|
| /external/llvm/test/Transforms/AddDiscriminators/ |
| D | oneline.ll | 42 ; CHECK: store i32 99, i32* %1, align 4, !dbg ![[COMBINE:[0-9]+]]
45 ; CHECK: br label %10, !dbg ![[COMBINE]]
97 ; CHECK: ![[COMBINE]] = !DILocation(line: 2, column: 42, scope: ![[COMBINEBLOCK:[0-9]+]])
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/AddDiscriminators/ |
| D | oneline.ll | 42 ; CHECK: store i32 99, i32* %1, align 4, !dbg ![[COMBINE:[0-9]+]]
45 ; CHECK: br label %10, !dbg ![[COMBINE]]
100 ; CHECK: ![[COMBINE]] = !DILocation(line: 2, column: 42, scope: ![[COMBINEBLOCK:[0-9]+]])
|
| /external/icu/icu4c/source/common/ |
| D | ushape.cpp | 60 #define COMBINE (SHADDA+CSHADDA) macro
1522 … if (aggregate_tashkeel && ((prevLink|currLink)&COMBINE) == COMBINE && aggregation_possible) { in u_shapeArabic()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 51 COMBINE, enumerator
|
| D | HexagonISelLowering.cpp | 1382 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2); in LowerLOAD()
2202 case HexagonISD::COMBINE: return "HexagonISD::COMBINE"; in getTargetNodeName()
2435 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0); in LowerBUILD_VECTOR()
2441 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0); in LowerBUILD_VECTOR()
2513 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand); in LowerBUILD_VECTOR()
2547 return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0); in LowerCONCAT_VECTORS()
2578 OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN); in LowerCONCAT_VECTORS()
2704 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val); in LowerINSERT_VECTOR()
|
| D | HexagonInstrInfo.td | 115 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1704 case HexagonISD::COMBINE: return "HexagonISD::COMBINE"; in getTargetNodeName()
2019 SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl, in LowerVECTOR_SHUFFLE()
2026 SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl, in LowerVECTOR_SHUFFLE()
2297 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L}); in buildVector64()
2413 ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in insertVector()
2544 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1), in LowerCONCAT_VECTORS()
2568 W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
2594 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
|
| D | HexagonISelLowering.h | 55 COMBINE, enumerator
|
| D | HexagonISelLoweringHVX.cpp | 730 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0}); in extractHvxSubvectorReg()
793 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0}); in extractHvxSubvectorPred()
|
| D | HexagonPatterns.td | 942 def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 1124 def COMBINE : NoTestOpInst<"vcombine", "kdd", "dPl", OP_CONC>;
|