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Searched refs:CONFIG_DDR_PLL2 (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/arch/arm/cpu/arm926ejs/spear/
Dspr600_mt47h32m16_333_cl5_psync.c9 #if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
12 #if (CONFIG_DDR_PLL2)
Dspr600_mt47h64m16_3_333_cl5_psync.c9 #if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
12 #if (CONFIG_DDR_PLL2)
Dspr600_mt47h128m8_3_266_cl5_async.c9 #if (CONFIG_DDR_PLL2)
Dspear600.c84 #elif (CONFIG_DDR_PLL2) in plat_ddr_init()
Dspl.c38 #elif (CONFIG_DDR_PLL2) in ddr_clock_init()
/external/u-boot/include/configs/
Dx600.h230 #define CONFIG_DDR_PLL2 0 macro
/external/u-boot/scripts/
Dconfig_whitelist.txt341 CONFIG_DDR_PLL2