| /external/u-boot/arch/x86/include/asm/ |
| D | cache.h | 13 #ifndef CONFIG_SYS_CACHELINE_SIZE
14 #define CONFIG_SYS_CACHELINE_SIZE 64 macro
17 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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| /external/u-boot/arch/arm/cpu/pxa/ |
| D | cache.c | 25 start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); in invalidate_dcache_range()
26 stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); in invalidate_dcache_range()
30 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
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| /external/u-boot/arch/powerpc/lib/ |
| D | cache.c | 16 start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); in flush_cache()
20 addr += CONFIG_SYS_CACHELINE_SIZE) { in flush_cache()
28 addr += CONFIG_SYS_CACHELINE_SIZE) { in flush_cache()
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| /external/u-boot/arch/riscv/include/asm/ |
| D | cache.h | 15 #ifdef CONFIG_SYS_CACHELINE_SIZE
16 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
| /external/u-boot/arch/microblaze/include/asm/ |
| D | cache.h | 15 #ifdef CONFIG_SYS_CACHELINE_SIZE
16 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
| /external/u-boot/arch/arm/cpu/arm926ejs/ |
| D | cache.c | 33 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
44 start += CONFIG_SYS_CACHELINE_SIZE; in flush_dcache_range()
|
| /external/u-boot/arch/arm/cpu/arm11/ |
| D | cpu.c | 73 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
84 start += CONFIG_SYS_CACHELINE_SIZE; in flush_dcache_range()
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| /external/u-boot/arch/nds32/include/asm/ |
| D | cache.h | 57 #ifdef CONFIG_SYS_CACHELINE_SIZE
58 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
| /external/u-boot/arch/arm/mach-omap2/omap5/ |
| D | sec_entry_cpu1.S | 84 mov r1, #CONFIG_SYS_CACHELINE_SIZE
113 .balign CONFIG_SYS_CACHELINE_SIZE
114 .rept CONFIG_SYS_CACHELINE_SIZE/4
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| /external/u-boot/arch/arm/lib/ |
| D | cache.c | 52 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) in check_cache_range()
55 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) in check_cache_range()
|
| D | cache-cp15.c | 82 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); in mmu_set_region_dcache_behaviour()
84 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); in mmu_set_region_dcache_behaviour()
|
| /external/u-boot/arch/powerpc/include/asm/ |
| D | cache.h | 31 #ifndef CONFIG_SYS_CACHELINE_SIZE
32 #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES macro
|
| /external/u-boot/arch/m68k/include/asm/ |
| D | cache.h | 197 #ifdef CONFIG_SYS_CACHELINE_SIZE
198 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
| /external/u-boot/drivers/net/ |
| D | fsl_mcdmafec.c | 509 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, in mcdmafec_initialize()
538 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcdmafec_initialize()
541 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcdmafec_initialize()
544 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); in mcdmafec_initialize()
552 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); in mcdmafec_initialize()
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| D | mcffec.c | 548 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, in mcffec_initialize()
577 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcffec_initialize()
580 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcffec_initialize()
583 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); in mcffec_initialize()
591 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); in mcffec_initialize()
|
| /external/u-boot/arch/sandbox/include/asm/ |
| D | cache.h | 22 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN macro
|
| /external/u-boot/arch/mips/include/asm/ |
| D | cache.h | 19 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN macro
|
| /external/u-boot/include/configs/ |
| D | rk3368_common.h | 11 #define CONFIG_SYS_CACHELINE_SIZE 64 macro
|
| D | rk3188_common.h | 9 #define CONFIG_SYS_CACHELINE_SIZE 64 macro
|
| D | mx7ulp_evk.h | 67 #define CONFIG_SYS_CACHELINE_SIZE 64 macro
|
| D | amcore.h | 91 #define CONFIG_SYS_CACHELINE_SIZE 16 macro
|
| /external/u-boot/arch/arm/include/asm/ |
| D | cache.h | 50 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
| /external/u-boot/drivers/usb/dwc3/ |
| D | io.h | 22 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
|
| /external/u-boot/drivers/fpga/ |
| D | zynqmppl.c | 236 ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE)); in zynqmp_loads()
246 CONFIG_SYS_CACHELINE_SIZE)); in zynqmp_loads()
|
| /external/u-boot/arch/arm/cpu/armv7/ |
| D | virt-v7.c | 56 unsigned long szflush = ALIGN(sz + 1, CONFIG_SYS_CACHELINE_SIZE); in relocate_secure_section()
|