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Searched refs:CONFIG_SYS_DDR_BLOCK2_BASE (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/include/configs/
Dls1012a_common.h25 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL macro
Dls2080a_common.h47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL macro
Dls1088a_common.h53 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL macro
Dls1046a_common.h43 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL macro
Dls1043a_common.h45 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL macro
/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dcpu.c754 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; in dram_init_banksize()
906 CONFIG_SYS_DDR_BLOCK2_BASE, in update_early_mmu_table()
925 CONFIG_SYS_DDR_BLOCK2_BASE, in update_early_mmu_table()
/external/u-boot/scripts/
Dconfig_whitelist.txt2380 CONFIG_SYS_DDR_BLOCK2_BASE