Home
last modified time | relevance | path

Searched refs:CONFIG_SYS_DDR_SDRAM_CLK_CNTL (Results 1 – 23 of 23) sorted by relevance

/external/u-boot/board/gdsys/mpc8308/
Dsdram.c47 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
/external/u-boot/board/freescale/mpc8308rdb/
Dsdram.c46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
/external/u-boot/board/mpc8308_p1m/
Dsdram.c42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
/external/u-boot/board/freescale/mpc8315erdb/
Dsdram.c63 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
/external/u-boot/include/configs/km/
Dkm83xx-common.h43 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ macro
/external/u-boot/board/freescale/mpc837xerdb/
Dmpc837xerdb.c104 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
/external/u-boot/board/freescale/mpc8349itx/
Dmpc8349itx.c67 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
/external/u-boot/include/configs/
Dmpc8308_p1m.h122 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
DMPC8308RDB.h121 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
DMPC8569MDS.h102 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 macro
DMPC8315ERDB.h95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
Dvme8349.h88 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
Dsbc8349.h78 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ macro
DMPC837XEMDS.h110 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
Dhrcon.h109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
DMPC8349ITX.h165 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
DMPC8349EMDS.h83 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
Dstrider.h109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
DMPC837XERDB.h133 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 macro
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dspd_sdram.c761 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ in spd_sdram()
762 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in spd_sdram()
/external/u-boot/board/freescale/mpc837xemds/
Dmpc837xemds.c264 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
/external/u-boot/board/freescale/mpc8569mds/
Dmpc8569mds.c250 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
/external/u-boot/scripts/
Dconfig_whitelist.txt2461 CONFIG_SYS_DDR_SDRAM_CLK_CNTL