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Searched refs:CONFIG_SYS_DDR_TIMING_3_1333 (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/board/freescale/bsc9132qds/
Dspl_minimal.c48 __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3); in sdram_init()
Dddr.c48 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
/external/u-boot/include/configs/
DBSC9132QDS.h161 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 macro
/external/u-boot/scripts/
Dconfig_whitelist.txt2491 CONFIG_SYS_DDR_TIMING_3_1333