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Searched refs:CONFIG_SYS_PCIE1_MEM_PHYS (Results 1 – 25 of 72) sorted by relevance

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/external/u-boot/board/varisys/cyrus/
Dtlb.c59 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
65 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
70 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/external/u-boot/board/freescale/t4rdb/
Dtlb.c55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
61 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
66 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/external/u-boot/board/freescale/t4qds/
Dtlb.c68 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
74 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
79 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/external/u-boot/board/freescale/common/p_corenet/
Dtlb.c94 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
100 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
105 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/external/u-boot/include/configs/
Dxpedite517x.h282 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
347 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
351 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
355 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
Dsbc8641d.h265 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
354 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
357 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Dcontrolcenterd.h226 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
229 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
DMPC8548CDS.h354 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull macro
357 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 macro
Dcyrus.h247 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
250 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
DMPC8572DS.h423 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
426 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
DP2041RDB.h378 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
381 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
DP1022DS.h415 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
418 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
DMPC8536DS.h414 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull macro
417 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 macro
Dcorenet_ds.h386 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
389 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
DMPC8641HPCN.h299 #define CONFIG_SYS_PCIE1_MEM_PHYS \ macro
327 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
/external/u-boot/board/gdsys/p1022/
Dtlb.c52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
56 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
/external/u-boot/board/xes/xpedite537x/
Dtlb.c54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
/external/u-boot/board/freescale/mpc8569mds/
Dtlb.c60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
69 (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
/external/u-boot/board/xes/xpedite550x/
Dtlb.c54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
/external/u-boot/board/freescale/b4860qds/
Dtlb.c66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
71 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
/external/u-boot/board/mpc8308_p1m/
Dmpc8308_p1m.c28 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
/external/u-boot/board/freescale/p1_twr/
Dtlb.c54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/external/u-boot/board/freescale/p1010rdb/
Dtlb.c55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/external/u-boot/board/freescale/c29xpcie/
Dtlb.c38 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/external/u-boot/board/Arcturus/ucp1020/
Dtlb.c52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,

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