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Searched refs:CONV (Results 1 – 25 of 53) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
D	store_fptoi.ll	`20 ; CHECK: xscvdpsxds [[CONV:[0-9]+]], [[LD]] 21 ; CHECK-NEXT: stxsd [[CONV]], 0(4) 26 ; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] 27 ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4 41 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] 42 ; CHECK-NEXT: stfiwx [[CONV]], 0, 4 47 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] 48 ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4 62 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] 63 ; CHECK-NEXT: stxsihx [[CONV]], 0, 4 [all …]`
D	f128-conv.ll	`21 ; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]] 22 ; CHECK-NEXT: stxv v[[CONV]], 0(r3) 39 ; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]] 40 ; CHECK-NEXT: stxv v[[CONV]], 0(r3) 55 ; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]] 56 ; CHECK-NEXT: stxv v[[CONV]], 0(r3) 69 ; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]] 70 ; CHECK-NEXT: stxv v[[CONV]], 0(r3) 87 ; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG0]] 88 ; CHECK-NEXT: stxv v[[CONV]], 0(r3) [all …]`
D	f128-truncateNconv.ll	`20 ; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 21 ; CHECK-NEXT: mfvsrd r3, v[[CONV]] 39 ; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 40 ; CHECK-NEXT: stxsd v[[CONV]], 0(r3) 61 ; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 62 ; CHECK-NEXT: mfvsrd r3, v[[CONV]] 81 ; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 82 ; CHECK-NEXT: stxsd v[[CONV]], 0(r5) 99 ; CHECK: xscvqpsdz v[[CONV:[0-9]+]], 100 ; CHECK-NEXT: stxsdx v[[CONV]], r3, r4 [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
D	signed-div-rem.ll	14 ; CHECK-NEXT: [[CONV:%.]] = sext i8 %x to i32 15 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], 128 34 ; CHECK-NEXT: [[CONV:%.]] = sext i8 %x to i32 35 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], -128 54 ; CHECK-NEXT: [[CONV:%.]] = zext i8 %x to i32 55 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], 255 74 ; CHECK-NEXT: [[CONV:%.]] = zext i8 %x to i32 75 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], -255 165 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32 166 ; CHECK-NEXT: ret i32 [[CONV]] [all …]
D	shift-128-kb.ll	`9 ; CHECK: [[CONV:%.]] = zext i32 %IntegerBitWidth to i64 10 ; CHECK-NEXT: [[SUB:%.]] = sub i64 128, [[CONV]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D	fcmp.ll	`161 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 162 ; CHECK-NEXT: ret i32 [[CONV]] 173 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 174 ; CHECK-NEXT: ret i32 [[CONV]] 185 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 186 ; CHECK-NEXT: ret i32 [[CONV]] 197 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 198 ; CHECK-NEXT: ret i32 [[CONV]] 209 ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32 210 ; CHECK-NEXT: ret i32 [[CONV]] [all …]`
D	double-float-shrink-1.ll	26 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 27 ; CHECK-NEXT: [[CALL:%.]] = call fast double @acos(double [[CONV]]) 48 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 49 ; CHECK-NEXT: [[CALL:%.]] = call fast double @acosh(double [[CONV]]) 70 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 71 ; CHECK-NEXT: [[CALL:%.]] = call fast double @asin(double [[CONV]]) 92 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 93 ; CHECK-NEXT: [[CALL:%.]] = call fast double @asinh(double [[CONV]]) 114 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 115 ; CHECK-NEXT: [[CALL:%.*]] = call fast double @atan(double [[CONV]]) [all …]
D	2011-05-28-swapmulsub.ll	`9 ; CHECK-NEXT: [[CONV:%.]] = add i16 [[TMP1]], -2 10 ; CHECK-NEXT: ret i16 [[CONV]] 28 ; CHECK-NEXT: [[CONV:%.]] = shl i16 [[SUBA_TR]], 2 29 ; CHECK-NEXT: ret i16 [[CONV]] 50 ; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -28 51 ; CHECK-NEXT: ret i16 [[CONV]]`
D	rotate.ll	130 ; CHECK-NEXT: [[CONV:%.]] = zext i16 [[V:%.]] to i32 133 ; CHECK-NEXT: [[SHR:%.]] = lshr i32 [[CONV]], [[RSHAMTCONV]] 137 ; CHECK-NEXT: [[SHL:%.]] = shl i32 [[CONV]], [[LSHAMTCONV]] 157 ; CHECK-NEXT: [[CONV:%.]] = zext i8 [[V:%.]] to i32 160 ; CHECK-NEXT: [[SHR:%.]] = lshr i32 [[CONV]], [[RSHAMTCONV]] 164 ; CHECK-NEXT: [[SHL:%.]] = shl i32 [[CONV]], [[LSHAMTCONV]] 188 ; CHECK-NEXT: [[CONV:%.]] = zext i16 [[V:%.]] to i32 190 ; CHECK-NEXT: [[SHR:%.]] = lshr i32 [[CONV]], [[RSHAMT]] 193 ; CHECK-NEXT: [[SHL:%.]] = shl i32 [[CONV]], [[LSHAMT]] 211 ; CHECK-NEXT: [[CONV:%.]] = zext i8 [[V:%.]] to i32 [all …]
D	icmp-mul-zext.ll	`7 ; CHECK-NEXT: [[CONV:%.]] = zext i32 [[TMP0:%.]] to i64 13 ; CHECK-NEXT: [[MUL3:%.]] = mul nuw nsw i64 [[CONV]], [[CONV2]] 57 ; CHECK-NEXT: [[CONV:%.]] = zext i8 [[BETH:%.]] to i32 60 ; CHECK-NEXT: [[MUL:%.]] = mul nuw nsw i32 [[CONV]], [[CONV]]`
D	vector-casts.ll	31 ; CHECK-NEXT: [[CONV:%.]] = bitcast <4 x i32> [[AND]] to <2 x i64> 32 ; CHECK-NEXT: ret <2 x i64> [[CONV]] 47 ; CHECK-NEXT: [[CONV:%.]] = bitcast <4 x i32> [[OR]] to <2 x i64> 48 ; CHECK-NEXT: ret <2 x i64> [[CONV]] 66 ; CHECK-NEXT: [[CONV:%.]] = bitcast <4 x i32> [[AND]] to <2 x i64> 67 ; CHECK-NEXT: ret <2 x i64> [[CONV]] 84 ; CHECK-NEXT: [[CONV:%.]] = bitcast <4 x i32> [[AND]] to <2 x i64> 85 ; CHECK-NEXT: ret <2 x i64> [[CONV]] 102 ; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64> 103 ; CHECK-NEXT: ret <2 x i64> [[CONV]]
D	div-shift.ll	`7 ; CHECK-NEXT: [[CONV:%.]] = zext i16 [[X:%.]] to i32 9 ; CHECK-NEXT: [[D:%.]] = lshr i32 [[CONV]], [[TMP0]] 22 ; CHECK-NEXT: [[CONV:%.]] = zext <2 x i16> [[X:%.]] to <2 x i32> 24 ; CHECK-NEXT: [[D:%.]] = lshr <2 x i32> [[CONV]], [[TMP0]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/ExpandMemCmp/X86/
D	memcmp.ll	`424 ; ALL-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 425 ; ALL-NEXT: ret i32 [[CONV]] 451 ; X32-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 452 ; X32-NEXT: ret i32 [[CONV]] 475 ; X64_1LD-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 476 ; X64_1LD-NEXT: ret i32 [[CONV]] 495 ; X64_2LD-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 496 ; X64_2LD-NEXT: ret i32 [[CONV]] 513 ; ALL-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32 514 ; ALL-NEXT: ret i32 [[CONV]] [all …]`
/external/llvm/test/CodeGen/AMDGPU/
D	cvt_f32_ubyte.ll	`8 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]] 9 ; SI: buffer_store_dword [[CONV]], 148 ; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]] 149 ; SI: buffer_store_dword [[CONV]], 192 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] 193 ; SI: buffer_store_dword [[CONV]] 205 ; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] 206 ; SI: buffer_store_dword [[CONV]] 219 ; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] 220 ; SI: buffer_store_dword [[CONV]] [all …]`
/external/mesa3d/src/mesa/main/
D	format_utils.c	815 #define SWIZZLE_CONVERT_LOOP(DST_TYPE, DST_CHANS, SRC_TYPE, SRC_CHANS, CONV) \ argument 821 tmp[j] = CONV; \ 857 #define SWIZZLE_CONVERT(DST_TYPE, SRC_TYPE, CONV) \ argument 872 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 1, CONV); \ 875 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 2, CONV); \ 878 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 3, CONV); \ 881 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 4, CONV); \ 888 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 1, CONV); \ 891 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 2, CONV); \ 894 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 3, CONV); \ [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
D	cvt_f32_ubyte.ll	11 ; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]] 12 ; GCN: buffer_store_dword [[CONV]], 173 ; GCN-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]] 174 ; GCN: buffer_store_dword [[CONV]], 225 ; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] 226 ; GCN: buffer_store_dword [[CONV]] 240 ; GCN: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] 241 ; GCN: buffer_store_dword [[CONV]] 256 ; GCN: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] 257 ; GCN: buffer_store_dword [[CONV]] [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
D	cse.ll	69 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[N:%.]] to double 76 ; CHECK-NEXT: [[TMP3:%.]] = insertelement <4 x double> undef, double [[CONV]], i32 0 77 ; CHECK-NEXT: [[TMP4:%.]] = insertelement <4 x double> [[TMP3]], double [[CONV]], i32 1 78 ; CHECK-NEXT: [[TMP5:%.]] = insertelement <4 x double> [[TMP4]], double [[CONV]], i32 2 79 ; CHECK-NEXT: [[TMP6:%.]] = insertelement <4 x double> [[TMP5]], double [[CONV]], i32 3 200 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[N:%.]] to double 207 ; CHECK-NEXT: [[TMP3:%.]] = insertelement <4 x double> undef, double [[CONV]], i32 0 208 ; CHECK-NEXT: [[TMP4:%.]] = insertelement <4 x double> [[TMP3]], double [[CONV]], i32 1 209 ; CHECK-NEXT: [[TMP5:%.]] = insertelement <4 x double> [[TMP4]], double [[CONV]], i32 2 210 ; CHECK-NEXT: [[TMP6:%.]] = insertelement <4 x double> [[TMP5]], double [[CONV]], i32 3 [all …]
D	compare-reduce.ll	`12 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[N:%.]] to double 13 ; CHECK-NEXT: [[TMP0:%.]] = insertelement <2 x double> undef, double [[CONV]], i32 0 14 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <2 x double> [[TMP0]], double [[CONV]], i32 1`
D	in-tree-user.ll	`13 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[N:%.]] to double 14 ; CHECK-NEXT: [[TMP0:%.]] = insertelement <2 x double> undef, double [[CONV]], i32 0 15 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <2 x double> [[TMP0]], double [[CONV]], i32 1`
D	load-merge.ll	`13 ; CHECK-NEXT: [[CONV:%.]] = zext i8 [[TMP0]] to i32 18 ; CHECK-NEXT: [[OR:%.]] = or i32 [[SHL3]], [[CONV]]`
D	horizontal-list.ll	15 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[MUL]] to float 20 ; CHECK-NEXT: [[ADD:%.]] = fadd fast float [[TMP4]], [[CONV]] 30 ; CHECK-NEXT: [[ADD7:%.]] = fadd fast float [[ADD_3]], [[CONV]] 42 ; THRESHOLD-NEXT: [[CONV:%.]] = sitofp i32 [[MUL]] to float 47 ; THRESHOLD-NEXT: [[ADD:%.]] = fadd fast float [[TMP4]], [[CONV]] 57 ; THRESHOLD-NEXT: [[ADD7:%.]] = fadd fast float [[ADD_3]], [[CONV]] 99 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[MUL]] to float 103 ; CHECK-NEXT: [[ADD:%.]] = fadd fast float undef, [[CONV]] 120 ; CHECK-NEXT: [[OP_EXTRA:%.]] = fadd fast float [[TMP4]], [[CONV]] 130 ; THRESHOLD-NEXT: [[CONV:%.]] = sitofp i32 [[MUL]] to float [all …]
/external/llvm/test/Transforms/InstSimplify/
D	shift-128-kb.ll	`9 ; CHECK: [[CONV:%.]] = zext i32 %IntegerBitWidth to i64 10 ; CHECK-NEXT: [[SUB:%.]] = sub i64 128, [[CONV]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/AArch64/
D	pr36032.ll	`24 ; CHECK-NEXT: [[CONV:%.]] = and i32 [[F_0]], 65535 33 ; CHECK-NEXT: [[TMP3:%.]] = add i32 [[G_0]], [[CONV]] 50 ; CHECK-NEXT: [[TMP14:%.]] = add i32 [[G_0]], [[CONV]] 78 ; CHECK-NEXT: [[TMP20:%.]] = add i32 [[CONV]], [[TMP19]] 101 ; CHECK-NEXT: [[ADD5]] = add nuw nsw i32 [[CONV]], 4 106 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[CONV]], [[TMP29]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D	i386-shrink-wrapping.ll	`59 ; CHECK-NEXT: movsbl ([[E]]), [[CONV:%[a-z]+]] 60 ; CHECK-NEXT: movl $6, [[CONV:%[a-z]+]] 64 ; CHECK-NEXT: cmovnel {{%[a-z]+}}, [[CONV]]`
/external/llvm/test/CodeGen/X86/
D	i386-shrink-wrapping.ll	`59 ; CHECK-NEXT: movsbl ([[F]]), [[CONV:%[a-z]+]] 60 ; CHECK-NEXT: movl $6, [[CONV:%[a-z]+]] 64 ; CHECK-NEXT: cmovnel {{%[a-z]+}}, [[CONV]]`

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