Home
last modified time | relevance | path

Searched refs:CPU_CONFIGURATION_REG (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_init.c381 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
382 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
384 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
386 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
Dddr3_axp.h30 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) macro
/external/u-boot/drivers/ddr/marvell/a38x/
Dmv_ddr_plat.c1223 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1224 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1227 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1230 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
Dmv_ddr_plat.h71 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) macro