1 /******************************************************************************* 2 * Copyright 2009-2018 Intel Corporation 3 * All Rights Reserved. 4 * 5 * If this software was obtained under the Intel Simplified Software License, 6 * the following terms apply: 7 * 8 * The source code, information and material ("Material") contained herein is 9 * owned by Intel Corporation or its suppliers or licensors, and title to such 10 * Material remains with Intel Corporation or its suppliers or licensors. The 11 * Material contains proprietary information of Intel or its suppliers and 12 * licensors. The Material is protected by worldwide copyright laws and treaty 13 * provisions. No part of the Material may be used, copied, reproduced, 14 * modified, published, uploaded, posted, transmitted, distributed or disclosed 15 * in any way without Intel's prior express written permission. No license under 16 * any patent, copyright or other intellectual property rights in the Material 17 * is granted to or conferred upon you, either expressly, by implication, 18 * inducement, estoppel or otherwise. Any license under such intellectual 19 * property rights must be express and approved by Intel in writing. 20 * 21 * Unless otherwise agreed by Intel in writing, you may not remove or alter this 22 * notice or any other notice embedded in Materials by Intel or Intel's 23 * suppliers or licensors in any way. 24 * 25 * 26 * If this software was obtained under the Apache License, Version 2.0 (the 27 * "License"), the following terms apply: 28 * 29 * You may not use this file except in compliance with the License. You may 30 * obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 31 * 32 * 33 * Unless required by applicable law or agreed to in writing, software 34 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 35 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 36 * 37 * See the License for the specific language governing permissions and 38 * limitations under the License. 39 *******************************************************************************/ 40 41 // 42 // Intel(R) Integrated Performance Primitives (Intel(R) IPP) Cryptography 43 // 44 45 #ifndef __DISPATCHER_H__ 46 #define __DISPATCHER_H__ 47 48 #if defined( __cplusplus ) 49 extern "C" { 50 #endif 51 52 /* 53 Intel(R) IPP libraries and CPU features mask fitness. Implemented only for IA32 and Intel64 (emt) 54 */ 55 56 #if defined( _ARCH_IA32 ) 57 #define M5_FM ( 0 ) 58 #ifdef _IPP_QUARK 59 #define PX_FM ( 0 ) 60 #else 61 #define PX_FM ( ippCPUID_MMX | ippCPUID_SSE ) 62 #endif 63 #define W7_FM ( PX_FM | ippCPUID_SSE2 ) 64 #define V8_FM ( W7_FM | ippCPUID_SSE3 | ippCPUID_SSSE3 ) 65 #define S8_FM ( V8_FM | ippCPUID_MOVBE ) 66 #define P8_FM ( V8_FM | ippCPUID_SSE41 | ippCPUID_SSE42 | ippCPUID_AES | ippCPUID_CLMUL | ippCPUID_SHA ) 67 #define G9_FM ( P8_FM | ippCPUID_AVX | ippAVX_ENABLEDBYOS | ippCPUID_RDRAND | ippCPUID_F16C ) 68 #define H9_FM ( G9_FM | ippCPUID_MOVBE | ippCPUID_AVX2 | ippCPUID_ADCOX | ippCPUID_RDSEED | ippCPUID_PREFETCHW ) 69 #define I0_FM ( H9_FM | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512PF | ippCPUID_AVX512ER | ippAVX512_ENABLEDBYOS ) 70 #define S0_FM ( H9_FM | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512VL | ippCPUID_AVX512BW | ippCPUID_AVX512DQ | ippAVX512_ENABLEDBYOS ) 71 72 #elif defined (_ARCH_EM64T) 73 74 #define PX_FM ( ippCPUID_MMX | ippCPUID_SSE | ippCPUID_SSE2 ) 75 #define M7_FM ( PX_FM | ippCPUID_SSE3 ) 76 #define U8_FM ( M7_FM | ippCPUID_SSSE3 ) 77 #define N8_FM ( U8_FM | ippCPUID_MOVBE ) 78 #define Y8_FM ( U8_FM | ippCPUID_SSE41 | ippCPUID_SSE42 | ippCPUID_AES | ippCPUID_CLMUL | ippCPUID_SHA ) 79 #define E9_FM ( Y8_FM | ippCPUID_AVX | ippAVX_ENABLEDBYOS | ippCPUID_RDRAND | ippCPUID_F16C ) 80 #define L9_FM ( E9_FM | ippCPUID_MOVBE | ippCPUID_AVX2 | ippCPUID_ADCOX | ippCPUID_RDSEED | ippCPUID_PREFETCHW ) 81 #define N0_FM ( L9_FM | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512PF | ippCPUID_AVX512ER | ippAVX512_ENABLEDBYOS ) 82 #define K0_FM ( L9_FM | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512VL | ippCPUID_AVX512BW | ippCPUID_AVX512DQ | ippAVX512_ENABLEDBYOS ) 83 84 #elif defined (_ARCH_LRB2) 85 #define PX_FM ( ippCPUID_KNC ) 86 #else 87 #error undefined architecture 88 #endif 89 90 #define PX_MSK ( 0 ) 91 #define MMX_MSK ( ippCPUID_MMX ) 92 #define SSE_MSK ( MMX_MSK | ippCPUID_SSE ) 93 #define SSE2_MSK ( SSE_MSK | ippCPUID_SSE2 ) 94 #define SSE3_MSK ( SSE2_MSK | ippCPUID_SSE3 ) 95 #define SSSE3_MSK ( SSE3_MSK | ippCPUID_SSSE3 ) 96 #define ATOM_MSK ( SSE3_MSK | ippCPUID_SSSE3 | ippCPUID_MOVBE ) 97 #define SSE41_MSK ( SSSE3_MSK | ippCPUID_SSE41 ) 98 #define SSE42_MSK ( SSE41_MSK | ippCPUID_SSE42 ) 99 #define AVX_MSK ( SSE42_MSK | ippCPUID_AVX ) 100 #define AVX2_MSK ( AVX_MSK | ippCPUID_AVX2 ) 101 #define AVX3X_MSK ( AVX2_MSK | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512VL | ippCPUID_AVX512BW | ippCPUID_AVX512DQ ) 102 #define AVX3M_MSK ( AVX2_MSK | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512PF | ippCPUID_AVX512ER ) 103 104 #if defined( _ARCH_IA32 ) && !defined( OSX32 ) && !defined( ANDROID ) 105 enum lib_enum { 106 LIB_W7=0, LIB_S8=1, LIB_P8=2, LIB_G9=3, LIB_H9=4, LIB_NOMORE 107 }; 108 #define LIB_PX LIB_W7 109 #elif defined( OSX32 ) 110 enum lib_enum { 111 LIB_S8=0, LIB_P8=1, LIB_G9=2, LIB_H9=3, LIB_NOMORE 112 }; 113 #define LIB_PX LIB_S8 114 #define LIB_W7 LIB_S8 115 #elif defined( ANDROID ) && defined( _ARCH_IA32 ) 116 enum lib_enum { 117 LIB_S8=0, LIB_P8=1, LIB_G9=2, LIB_H9=3, LIB_NOMORE 118 }; 119 #define LIB_PX LIB_S8 120 #define LIB_W7 LIB_S8 121 122 #elif defined( ANDROID ) && defined( _ARCH_EM64T ) 123 enum lib_enum { 124 LIB_N8=0, LIB_Y8=1, LIB_E9=2, LIB_L9=3, LIB_NOMORE 125 }; 126 #define LIB_PX LIB_N8 127 #define LIB_M7 LIB_N8 128 #define LIB_K0 LIB_L9 129 #define LIB_N0 LIB_L9 130 131 #elif defined( _ARCH_EM64T ) && !defined( OSXEM64T ) && !defined( ANDROID ) && !defined( _WIN32E ) /* Linux* OS Intel64 supports N0 */ 132 enum lib_enum { 133 LIB_M7=0, LIB_N8=1, LIB_Y8=2, LIB_E9=3, LIB_L9=4, LIB_N0=5, LIB_K0=6, LIB_NOMORE 134 }; 135 #define LIB_PX LIB_M7 136 #elif defined( _ARCH_EM64T ) && !defined( OSXEM64T ) && !defined( ANDROID ) /* Windows* OS Intel64 doesn't support N0 */ 137 enum lib_enum { 138 LIB_M7=0, LIB_N8=1, LIB_Y8=2, LIB_E9=3, LIB_L9=4, LIB_K0=5, LIB_NOMORE 139 }; 140 #define LIB_PX LIB_M7 141 #define LIB_N0 LIB_L9 142 #elif defined( OSXEM64T ) 143 enum lib_enum { 144 LIB_N8=0, LIB_Y8=1, LIB_E9=2, LIB_L9=3, LIB_K0=4, LIB_NOMORE 145 }; 146 #define LIB_PX LIB_N8 147 #define LIB_M7 LIB_N8 148 #define LIB_N0 LIB_L9 149 #elif defined( _ARCH_LRB2 ) 150 enum lib_enum { 151 LIB_PX=0, LIB_B2=1, LIB_NOMORE 152 }; 153 #define LIB_MIC LIB_B2 154 #else 155 #error "lib_enum isn't defined!" 156 #endif 157 158 #if defined( _ARCH_IA32 ) 159 #if defined( OSX32 ) /* OSX supports starting with Intel(R) architecture formerly codenamed Penryn only */ 160 #define LIB_MMX LIB_S8 161 #define LIB_SSE LIB_S8 162 #define LIB_SSE2 LIB_S8 163 #define LIB_SSE3 LIB_S8 164 #define LIB_ATOM LIB_S8 165 #define LIB_SSSE3 LIB_S8 166 #define LIB_SSE41 LIB_S8 167 #define LIB_SSE42 LIB_P8 168 #define LIB_AVX LIB_G9 169 #define LIB_AVX2 LIB_H9 170 #define LIB_AVX3M LIB_H9 /* no ia32 library for Intel(R) Xeon Phi(TM) processor (formerly Knight Landing) */ 171 #define LIB_AVX3X LIB_H9 /* no ia32 library for Intel(R) Xeon(R) processor (formerly Skylake) */ 172 #else 173 #define LIB_MMX LIB_W7 174 #define LIB_SSE LIB_W7 175 #define LIB_SSE2 LIB_W7 176 #define LIB_SSE3 LIB_W7 177 #define LIB_ATOM LIB_S8 178 #define LIB_SSSE3 LIB_S8 179 #define LIB_SSE41 LIB_S8 /* P8 is oriented for new Intel Atom(R) processor (formerly Silvermont) */ 180 #define LIB_SSE42 LIB_P8 181 #define LIB_AVX LIB_G9 182 #define LIB_AVX2 LIB_H9 183 #define LIB_AVX3M LIB_H9 /* no ia32 library for Intel(R) Xeon Phi(TM) processor (formerly Knight Landing) */ 184 #define LIB_AVX3X LIB_H9 /* no ia32 library for Intel(R) Xeon(R) processor (formerly Skylake) */ 185 #endif 186 #elif defined (_ARCH_EM64T) 187 #if defined( OSXEM64T ) /* OSX supports starting PNR only */ 188 #define LIB_MMX LIB_N8 189 #define LIB_SSE LIB_N8 190 #define LIB_SSE2 LIB_N8 191 #define LIB_SSE3 LIB_N8 192 #define LIB_ATOM LIB_N8 193 #define LIB_SSSE3 LIB_N8 194 #define LIB_SSE41 LIB_N8 195 #define LIB_SSE42 LIB_Y8 196 #define LIB_AVX LIB_E9 197 #define LIB_AVX2 LIB_L9 198 #define LIB_AVX3M LIB_L9 199 #define LIB_AVX3X LIB_K0 200 #else 201 #define LIB_MMX LIB_M7 202 #define LIB_SSE LIB_M7 203 #define LIB_SSE2 LIB_M7 204 #define LIB_SSE3 LIB_M7 205 #define LIB_ATOM LIB_N8 206 #define LIB_SSSE3 LIB_N8 207 #define LIB_SSE41 LIB_N8 /* Y8 is oriented for new Intel Atom(R) processor (formerly Silvermont) */ 208 #define LIB_SSE42 LIB_Y8 209 #define LIB_AVX LIB_E9 210 #define LIB_AVX2 LIB_L9 211 #define LIB_AVX3M LIB_N0 212 #define LIB_AVX3X LIB_K0 213 #endif 214 #elif defined (_ARCH_LRB2) 215 #define LIB_MIC LIB_B2 216 #endif 217 218 #if defined( _IPP_DYNAMIC ) 219 #if defined( _ARCH_IA32 ) 220 221 /* Describe Intel CPUs and libraries */ 222 typedef enum{CPU_W7=0, CPU_S8, CPU_P8, CPU_G9, CPU_H9, CPU_NOMORE} cpu_enum; 223 typedef enum{DLL_W7=0, DLL_S8, DLL_P8, DLL_G9, DLL_H9, DLL_NOMORE} dll_enum; 224 225 /* New cpu can use some libraries for old cpu */ 226 static const dll_enum dllUsage[][DLL_NOMORE+1] = { 227 /* DLL_H9, DLL_G9, DLL_P8, DLL_S8, DLL_W7, DLL_NOMORE */ 228 /*CPU_W7*/ { DLL_W7, DLL_NOMORE }, 229 /*CPU_S8*/ { DLL_S8, DLL_W7, DLL_NOMORE }, 230 /*CPU_P8*/ { DLL_P8, DLL_S8, DLL_W7, DLL_NOMORE }, 231 /*CPU_G9*/ { DLL_G9, DLL_P8, DLL_S8, DLL_W7, DLL_NOMORE }, 232 /*CPU_H9*/ { DLL_H9, DLL_G9, DLL_P8, DLL_S8, DLL_W7, DLL_NOMORE } 233 }; 234 235 #elif defined (_ARCH_EM64T) 236 /* Describe Intel CPUs and libraries */ 237 typedef enum{CPU_M7=0, CPU_N8, CPU_Y8, CPU_E9, CPU_L9, CPU_N0, CPU_K0, CPU_NOMORE} cpu_enum; 238 typedef enum{DLL_M7=0, DLL_N8, DLL_Y8, DLL_E9, DLL_L9, DLL_N0, DLL_K0, DLL_NOMORE} dll_enum; 239 240 /* New cpu can use some libraries for old cpu */ 241 static const dll_enum dllUsage[][DLL_NOMORE+1] = { 242 /* DLL_K0, DLL_N0, DLL_L9, DLL_E9, DLL_Y8, DLL_N8, DLL_M7, DLL_NOMORE */ 243 /*CPU_M7*/ { DLL_M7, DLL_NOMORE }, 244 /*CPU_N8*/ { DLL_N8, DLL_M7, DLL_NOMORE }, 245 /*CPU_Y8*/ { DLL_Y8, DLL_N8, DLL_M7, DLL_NOMORE }, 246 /*CPU_E9*/ { DLL_E9, DLL_Y8, DLL_N8, DLL_M7, DLL_NOMORE }, 247 /*CPU_L9*/ { DLL_L9, DLL_E9, DLL_Y8, DLL_N8, DLL_M7, DLL_NOMORE }, 248 /*CPU_N0*/ { DLL_N0, DLL_L9, DLL_E9, DLL_Y8, DLL_N8, DLL_M7, DLL_NOMORE }, 249 /*CPU_K0*/ { DLL_K0, DLL_N0, DLL_L9, DLL_E9, DLL_Y8, DLL_N8, DLL_M7, DLL_NOMORE } 250 }; 251 252 #endif 253 254 #if defined( _PCS ) 255 256 /* Names of the Intel libraries which can be loaded */ 257 #if defined ( _WIN32 ) && !defined( _WIN64 ) && !defined( _WIN32E ) 258 static const _TCHAR* dllNames[DLL_NOMORE] = { 259 _T(IPP_LIB_PREFIX()) _T("w7") _T(".dll"), 260 _T(IPP_LIB_PREFIX()) _T("s8") _T(".dll"), 261 _T(IPP_LIB_PREFIX()) _T("p8") _T(".dll"), 262 _T(IPP_LIB_PREFIX()) _T("g9") _T(".dll"), 263 _T(IPP_LIB_PREFIX()) _T("h9") _T(".dll") 264 }; 265 #elif defined(linux32) 266 static const _TCHAR* dllNames[DLL_NOMORE] = { 267 _T("lib") _T(IPP_LIB_PREFIX()) _T("w7.so"), 268 _T("lib") _T(IPP_LIB_PREFIX()) _T("s8.so"), 269 _T("lib") _T(IPP_LIB_PREFIX()) _T("p8.so"), 270 _T("lib") _T(IPP_LIB_PREFIX()) _T("g9.so"), 271 _T("lib") _T(IPP_LIB_PREFIX()) _T("h9.so") 272 }; 273 #elif defined( OSX32 ) 274 static const _TCHAR* dllNames[DLL_NOMORE] = { 275 _T("lib") _T(IPP_LIB_PREFIX()) _T("s8") _T(".dylib"), 276 _T("lib") _T(IPP_LIB_PREFIX()) _T("p8") _T(".dylib"), 277 _T("lib") _T(IPP_LIB_PREFIX()) _T("g9") _T(".dylib"), 278 _T("lib") _T(IPP_LIB_PREFIX()) _T("h9") _T(".dylib") 279 }; 280 #elif defined( _WIN32E ) 281 static const _TCHAR* dllNames[DLL_NOMORE] = { 282 _T(IPP_LIB_PREFIX()) _T("m7") _T(".dll"), 283 _T(IPP_LIB_PREFIX()) _T("n8") _T(".dll"), 284 _T(IPP_LIB_PREFIX()) _T("y8") _T(".dll"), 285 _T(IPP_LIB_PREFIX()) _T("e9") _T(".dll"), 286 _T(IPP_LIB_PREFIX()) _T("l9") _T(".dll"), /* no support for N0 on win */ 287 _T(IPP_LIB_PREFIX()) _T("k0") _T(".dll") 288 }; 289 #elif defined( OSXEM64T ) 290 static const _TCHAR* dllNames[DLL_NOMORE] = { 291 _T("lib") _T(IPP_LIB_PREFIX()) _T("n8") _T(".dylib"), 292 _T("lib") _T(IPP_LIB_PREFIX()) _T("y8") _T(".dylib"), 293 _T("lib") _T(IPP_LIB_PREFIX()) _T("e9") _T(".dylib"), 294 _T("lib") _T(IPP_LIB_PREFIX()) _T("l9") _T(".dylib"), 295 _T("lib") _T(IPP_LIB_PREFIX()) _T("k0") _T(".dylib") 296 }; 297 #elif defined( linux32e ) 298 static const _TCHAR* dllNames[DLL_NOMORE] = { 299 _T("lib") _T(IPP_LIB_PREFIX()) _T("m7.so"), 300 _T("lib") _T(IPP_LIB_PREFIX()) _T("n8.so"), 301 _T("lib") _T(IPP_LIB_PREFIX()) _T("y8.so"), 302 _T("lib") _T(IPP_LIB_PREFIX()) _T("e9.so"), 303 _T("lib") _T(IPP_LIB_PREFIX()) _T("l9.so"), 304 _T("lib") _T(IPP_LIB_PREFIX()) _T("n0.so"), 305 _T("lib") _T(IPP_LIB_PREFIX()) _T("k0.so") 306 }; 307 #endif 308 309 #endif /* _PCS */ 310 311 #else /*_IPP_DYNAMIC */ 312 313 314 #endif 315 316 317 #if defined( __cplusplus ) 318 } 319 #endif 320 321 #endif /* __DISPATCHER_H__ */ 322