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Searched refs:CP_PACKET0 (Results 1 – 13 of 13) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state_init.c163 return CP_PACKET0(packet[id].start, packet[id].len - 1); in cmdpkt()
243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
375 OUT_BATCH(CP_PACKET0(packet[0].start, 3)); in ctx_emit_cs()
379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); in ctx_emit_cs()
382 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); in ctx_emit_cs()
386 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); in ctx_emit_cs()
388 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); in ctx_emit_cs()
393 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); in ctx_emit_cs()
[all …]
Dradeon_ioctl.c102 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
104 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeonEmitScissor()
107 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeonEmitScissor()
113 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
Dradeon_cmdbuf.h19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
Dradeon_context.c116 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); in r100_emit_query_finish()
Dradeon_blit.c37 return CP_PACKET0(reg, count - 1); in cmdpacket0()
/external/mesa3d/src/gallium/drivers/r300/
Dr300_cb.h132 OUT_CB(CP_PACKET0(register, 0)); \
140 OUT_CB(CP_PACKET0(register, (count) - 1)); \
145 OUT_CB(CP_PACKET0(register, (count) - 1) | RADEON_ONE_REG_WR); \
Dr300_cs.h83 OUT_CS(CP_PACKET0(register, 0)); \
90 OUT_CS(CP_PACKET0((register), ((count) - 1)))
93 OUT_CS(CP_PACKET0((register), ((count) - 1)) | RADEON_ONE_REG_WR)
Dr300_reg.h3544 #define CP_PACKET0(register, count) \ macro
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_state_init.c168 return CP_PACKET0(packet[id].start, packet[id].len - 1); in cmdpkt()
281 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
283 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
297 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
299 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
310 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
319 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
493 OUT_BATCH(CP_PACKET0(packet[0].start, 3)); in ctx_emit_cs()
497 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); in ctx_emit_cs()
500 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); in ctx_emit_cs()
[all …]
Dradeon_cmdbuf.h19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
Dr200_context.c151 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); in r200_emit_query_finish()
Dr200_blit.c37 return CP_PACKET0(reg, count - 1); in cmdpacket0()
Dr200_cmdbuf.c215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0)); in r200EmitMaxVtxIndex()