| /external/u-boot/board/renesas/sh7757lcr/ |
| D | spi-boot.c | 32 #define CR2 0xFE002010 macro
74 spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ in spi_reset()
75 spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); in spi_reset()
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| /external/u-boot/board/renesas/sh7752evb/ |
| D | spi-boot.c | 28 #define CR2 0xFE002010 macro
77 spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ in spi_reset()
78 spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); in spi_reset()
|
| /external/u-boot/board/renesas/sh7753evb/ |
| D | spi-boot.c | 24 #define CR2 0xFE002010 macro
82 spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ in spi_reset()
83 spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); in spi_reset()
|
| /external/syzkaller/pkg/report/testdata/linux/report/ |
| D | 112 | 27 [ 190.154802] CR2: 0000000000000286 CR3: 00000001d91cf000 CR4: 00000000001426e0
35 [ 190.154802] CR2: 0000000000000286
|
| D | 247 | 20 [ 61.895826] CR2: 0000000000000000 CR3: 0000000073729000 CR4: 00000000000006e0
39 [ 61.895826] CR2: 0000000000000000
|
| D | 256 | 19 [ 27.493252] CR2: ffffffffffffffd6 CR3: 00000001b5858000 CR4: 00000000001406e0
100 [ 27.879706] CR2: 0000000000000000
112 [ 27.951941] CR2: ffffffffffffffd6 CR3: 00000001b5858000 CR4: 00000000001406e0
|
| D | 175 | 21 [ 83.564444] CR2: ffffffffffffffd8 CR3: 00000001ffb69003 CR4: 00000000001626f0
35 [ 83.657187] CR2: ffffffffffffffd8
|
| D | 114 | 27 [ 161.631524] CR2: 0000000000000074 CR3: 00000001c6768000 CR4: 00000000001426e0
43 [ 161.632233] CR2: 0000000000000074
|
| D | 139 | 24 [ 70.858151] CR2: ffff880214d12c00 CR3: 00000001dd63c000 CR4: 00000000001406f0
51 [ 71.008876] CR2: ffff880214d12c00
|
| D | 146 | 21 [ 19.572719] CR2: 0000000100000137 CR3: 000000000301e003 CR4: 00000000001606e0
52 [ 19.572868] CR2: 0000000100000137
|
| D | 167 | 27 [ 522.327365] CR2: ffffc90001691000 CR3: 00000001ccefa005 CR4: 00000000001606e0
63 [ 522.518301] CR2: ffffc90001691000
|
| D | 160 | 26 [ 190.757101] CR2: ffffffffffffffff CR3: 0000000007e0f000 CR4: 00000000001406e0
106 [ 190.757101] CR2: ffffffffffffffff
|
| D | 174 | 21 [ 219.058867] CR2: 0000000000000010 CR3: 000000020f0fe005 CR4: 00000000001606f0
66 [ 219.245420] CR2: 0000000000000010
|
| D | 260 | 20 [ 242.933400] CR2: 00007f0b2981bdb8 CR3: 000000019c56e000 CR4: 00000000001406f0
109 [ 243.415667] CR2: 00007f0b2981bdb8 CR3: 000000019c56e000 CR4: 00000000001406f0
|
| D | 50 | 20 [ 1722.511384] CR2: 00000000205fb000 CR3: 0000000032467000 CR4: 00000000000006e0
|
| D | 14 | 20 [ 1722.511384] CR2: 000000002095f000 CR3: 0000000062876000 CR4: 00000000000006f0
|
| D | 44 | 19 [ 34.623698] CR2: 00000000004c4b90 CR3: 00000001ce6eb000 CR4: 00000000001426f0
|
| /external/syzkaller/pkg/report/testdata/fuchsia/report/ |
| D | 3 | 22 CS: 0x10 RIP: 0xffffffff00118e64 EFL: 0x10293 CR2: 0x8
59 CS: 0x10 RIP: 0xffffffff00118e64 EFL: 0x10293 CR2: 0x8
|
| D | 5 | 10 CS: 0x10 RIP: 0xffffffff001a1f12 EFL: 0x10006 CR2: 0xffffff9bf8dab000
|
| D | 7 | 13 CS: 0x33 RIP: 0x2c3a222b7a30 EFL: 0x10202 CR2: 0xfffffffffffffff8
|
| D | 0 | 28 CS: 0x10 RIP: 0xffffffff801066f3 EFL: 0x10006 CR2: 0x38
49 CS: 0x10 RIP: 0xffffffff801a41a7 EFL: 0x10202 CR2: 0xb0
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 159 {PPC::CR2, -4}, in getCalleeSavedSpillSlots()
1069 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) in emitPrologue()
1075 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in emitPrologue()
1079 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; in emitPrologue()
1433 (SavedRegs.test(PPC::CR2) || in determineCalleeSaves()
1626 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) in processFunctionBeforeFrameFinalized()
1738 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; in spillCalleeSavedRegisters()
1802 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) in restoreCRs()
1890 if (Reg == PPC::CR2) { in restoreCalleeSavedRegisters()
1906 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in restoreCalleeSavedRegisters()
|
| D | PPCCallingConv.td | 226 F27, F28, F29, F30, F31, CR2, CR3, CR4
235 F27, F28, F29, F30, F31, CR2, CR3, CR4
244 F27, F28, F29, F30, F31, CR2, CR3, CR4
253 F27, F28, F29, F30, F31, CR2, CR3, CR4
|
| /external/syzkaller/pkg/report/testdata/linux/guilty/ |
| D | 18 | 25 CR2: 0000000000000074 CR3: 00000001c6f12000 CR4: 00000000001406e0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 159 {PPC::CR2, -4}, in getCalleeSavedSpillSlots()
1198 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) in emitPrologue()
1204 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in emitPrologue()
1208 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; in emitPrologue()
1658 (SavedRegs.test(PPC::CR2) || in determineCalleeSaves()
1859 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) in processFunctionBeforeFrameFinalized()
1976 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; in spillCalleeSavedRegisters()
2050 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) in restoreCRs()
2136 if (Reg == PPC::CR2) { in restoreCalleeSavedRegisters()
2152 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in restoreCalleeSavedRegisters()
|