| /external/u-boot/board/renesas/sh7753evb/ |
| D | spi-boot.c | 27 #define CR7 0xFE002038 macro
91 spi_write(CR7_IDX_OR12, CR7); in spi_read_flash()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 171 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
183 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
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| D | PPCBaseInfo.h | 38 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; in getPPCRegisterNumbering()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCCodeEmitter.cpp | 142 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
252 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
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| D | PPCRegisterInfo.td | 246 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
317 CR7, CR2, CR3, CR4)> {
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| D | PPCInstrInfo.cpp | 446 Reg = PPC::CR7; in StoreRegToStackSlot()
575 Reg = PPC::CR7; in LoadRegFromStackSlot()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ipra-reg-usage.ll | 6 …S FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 BND3 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 C…
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 51 Reg = PPC::CR7; in getCRFromCRBit()
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| D | PPCRegisterInfo.td | 201 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
345 CR7, CR2, CR3, CR4)>;
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| D | PPCInstr64Bit.td | 979 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
988 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1011 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1020 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 51 Reg = PPC::CR7; in getCRFromCRBit()
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| D | PPCRegisterInfo.td | 209 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
370 CR7, CR2, CR3, CR4)>;
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| D | PPCInstr64Bit.td | 1097 let isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in
1117 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1126 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1149 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1158 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 349 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
363 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 353 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
366 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 186 case PPC::CR7: RegNo = 7; break; in printcrbitm()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 268 ENTRY(CR7) \
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 368 case PPC::CR7: RegNo = 7; break; in printcrbitm()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 411 case PPC::CR7: RegNo = 7; break; in printcrbitm()
|
| /external/capstone/arch/X86/ |
| D | X86DisassemblerDecoder.h | 368 ENTRY(CR7) \
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 362 ENTRY(CR7) \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 362 ENTRY(CR7) \
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 218 case X86::CR7: case X86::CR15: case X86::DR7: return 7; in getX86RegNum()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 37 CR7 = 18,
266 const unsigned CR7_Overlaps[] = { X86::CR7, 0 };
583 { "CR7", CR7_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
800 …X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9…
1450 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, false );
1611 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, false );
1772 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, false );
1938 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, true );
2099 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, true );
2260 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, true );
[all …]
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
|