Searched refs:CRRegs (Results 1 – 7 of 7) sorted by relevance
| /external/capstone/arch/PowerPC/ |
| D | PPCDisassembler.c | 36 static const unsigned CRRegs[] = { variable
165 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
324 MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]); in decodeCRBitMOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | circ_ldd_bug.ll | 10 ; %0 (CRRegs) = TFCR %0 (IntRegs)
12 ; %1 (CRRegs) = TFCR %1 (IntRegs)
14 ; The scheduler would move the CRRegs to the top of the loop. The allocator
15 ; would try to spill the CRRegs after running out of them. We don't have code to
16 ; spill CRRegs and the above assertion would be triggered.
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 65 static const unsigned CRRegs[] = { variable
218 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
224 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRC0RegisterClass()
393 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | circ_ldd_bug.ll | 10 ; %vreg0 (CRRegs) = TFCR %vreg0 (IntRegs)
12 ; %vreg1 (CRRegs) = TFCR %vreg1 (IntRegs)
14 ; The scheduler would move the CRRegs to the top of the loop. The allocator
15 ; would try to spill the CRRegs after running out of them. We don't have code to
16 ; spill CRRegs and the above assertion would be triggered.
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 65 static const unsigned CRRegs[] = { variable
251 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
257 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRC0RegisterClass()
495 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 193 static const MCPhysReg CRRegs[8] = { variable
678 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); in addRegCRRCOperands()
683 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); in addCRBitMaskOperands()
1366 RegNo = CRRegs[IntVal]; in MatchRegisterName()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 173 static const MCPhysReg CRRegs[8] = { variable
641 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); in addRegCRRCOperands()
646 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); in addCRBitMaskOperands()
1305 RegNo = CRRegs[IntVal]; in MatchRegisterName()
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