CRn (reference) in projects: external - OpenGrok search results

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Searched refs:CRn (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/AArch64/Utils/
D	AArch64BaseInfo.cpp	`93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local 97 Ops[3].getAsInteger(10, CRn); in parseGenericRegister() 100 Bits = (Op0 << 14) \| (Op1 << 11) \| (CRn << 7) \| (CRm << 3) \| Op2; in parseGenericRegister() 109 uint32_t CRn = (Bits >> 7) & 0xf; in genericRegisterString() local 113 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/
D	AArch64BaseInfo.cpp	`122 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local 126 Ops[3].getAsInteger(10, CRn); in parseGenericRegister() 129 Bits = (Op0 << 14) \| (Op1 << 11) \| (CRn << 7) \| (CRm << 3) \| Op2; in parseGenericRegister() 138 uint32_t CRn = (Bits >> 7) & 0xf; in genericRegisterString() local 142 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()`
/external/capstone/arch/AArch64/
D	AArch64BaseInfo.c	`633 uint32_t Op0, Op1, CRn, CRm, Op2; in A64SysRegMapper_toString() local 670 CRn = (Bits >> 7) & 0xf; in A64SysRegMapper_toString() 676 if (Op0 != 3 \|\| (CRn != 11 && CRn != 15)) { in A64SysRegMapper_toString() 686 CRnS = utostr(CRn, false); in A64SysRegMapper_toString()`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
D	AArch64SystemOperands.td	`371 // op1 CRn CRm op2 390 // op1 CRn CRm op2 469 // Op0 Op1 CRn CRm Op2 530 // Op0 Op1 CRn CRm Op2 569 // Op0 Op1 CRn CRm Op2 580 // Op0 Op1 CRn CRm Op2 586 // Op0 Op1 CRn CRm Op2 591 // Op0 Op1 CRn CRm Op2 601 // Op0 Op1 CRn CRm Op2 607 // Op0 Op1 CRn CRm Op2 [all …]`
D	AArch64InstrFormats.td	`1118 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.`
/external/llvm/lib/Target/AArch64/
D	AArch64SystemOperands.td	`311 // Op0 Op1 CRn CRm Op2 366 // Op0 Op1 CRn CRm Op2 405 // Op0 Op1 CRn CRm Op2 416 // Op0 Op1 CRn CRm Op2 421 // Op0 Op1 CRn CRm Op2 431 // Op0 Op1 CRn CRm Op2 437 // Op0 Op1 CRn CRm Op2 442 // Op0 Op1 CRn CRm Op2 454 // Op0 Op1 CRn CRm Op2 709 // Op0 Op1 CRn CRm Op2 [all …]`
D	AArch64InstrFormats.td	`896 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
D	ARMInstrThumb2.td	4143 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4154 bits<4> CRn; 4161 let Inst{19-16} = CRn; 4191 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4193 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4196 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4197 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4200 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4202 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4206 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm", [all …]
D	ARMInstrInfo.td	`5079 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5080 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5081 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5085 bits<4> CRn; 5096 let Inst{19-16} = CRn; 5103 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5104 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5105 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5110 bits<4> CRn; 5121 let Inst{19-16} = CRn; [all …]`
/external/llvm/lib/Target/ARM/
D	ARMInstrThumb2.td	4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4162 bits<4> CRn; 4169 let Inst{19-16} = CRn; 4195 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4197 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4200 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4201 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4204 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4206 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4210 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm", [all …]
D	ARMInstrInfo.td	`4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4815 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4819 bits<4> CRn; 4830 let Inst{19-16} = CRn; 4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4837 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4842 bits<4> CRn; 4853 let Inst{19-16} = CRn; [all …]`
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
D	ARMInstrThumb2.td	3620 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), 3631 bits<4> CRn; 3638 let Inst{19-16} = CRn; 3666 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3668 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3671 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3673 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3678 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3682 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3685 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), [all …]
D	ARMInstrInfo.td	`4215 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4217 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4220 bits<4> CRn; 4231 let Inst{19-16} = CRn; 4236 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4238 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4242 bits<4> CRn; 4253 let Inst{19-16} = CRn; [all …]`
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
D	ARMGenGlobalISel.inc	20526 …CRn, (imm:{ :[i32] }):$CRm, (imm:{ :[i32] }):$opc2) => (CDP (imm:{ :[i32] }):$cop, (imm:{ :[… 20531 GIR_CopyConstantAsSImm, /NewInsnID/0, /OldInsnID/4, // CRn 20581 …CRn, (imm:{ :[i32] }):$CRm, (imm:{ :[i32] }):$opc2) => (CDP2 (imm:{ :[i32] }):$cop, (imm:{ :… 20586 GIR_CopyConstantAsSImm, /NewInsnID/0, /OldInsnID/4, // CRn 20634 …CRn, (imm:{ :[i32] }):$CRm, (imm:{ :[i32] }):$opc2) => (t2CDP (imm:{ :[i32] }):$cop, (imm:{ … 20639 GIR_CopyConstantAsSImm, /NewInsnID/0, /OldInsnID/4, // CRn 20689 …CRn, (imm:{ :[i32] }):$CRm, (imm:{ :[i32] }):$opc2) => (t2CDP2 (imm:{ :[i32] }):$cop, (imm:{ … 20694 GIR_CopyConstantAsSImm, /NewInsnID/0, /OldInsnID/4, // CRn 20740 …):$CRn, (imm:{ :[i32] }):$CRm, (imm:{ :[i32] }):$opc2) => (MRC:{ :[i32] } (imm:{ :[i32] }):$… 20745 GIR_CopyConstantAsSImm, /NewInsnID/0, /OldInsnID*/3, // CRn [all …]
D	ARMGenDAGISel.inc	10029 /* 21351/ OPC_RecordChild5, // #4 = $CRn 10054 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ :[i32] }):… 10055 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ :[i32] }):… 10069 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ :[i32] }):… 10070 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ :[i32] }):… 10086 / 21463/ OPC_RecordChild5, // #4 = $CRn 10109 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ :[i32] }):… 10110 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ :[i32] }):… 10124 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ :[i32] }):… 10125 …:$cop, (imm:{ :[i32] }):$opc1, (imm:{ :[i32] }):$CRd, (imm:{ :[i32] }):$CRn, (imm:{ *:[i32] }):… [all …]
D	ARMGenMCCodeEmitter.inc	`4527 // op: CRn 4677 // op: CRn 8409 // op: CRn 10712 // op: CRn 10788 // op: CRn 10800 // op: CRn`
/external/capstone/arch/ARM/
D	ARMGenAsmWriter.inc	8878 // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 8889 // (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0) 8933 // (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 8944 // (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0) 10906 // (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 10917 // (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 10937 // (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 10948 // (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
/external/v8/src/arm64/
D	constants-arm64.h	`246 V_(CRn, 15, 12, Bits) \`
/external/vixl/src/aarch64/
D	constants-aarch64.h	`139 V_(CRn, 15, 12, ExtractBits) \`
D	assembler-aarch64.h	`3772 static Instr CRn(int imm4) { in CRn() function`
D	assembler-aarch64.cc	`1757 Emit(SYS \| ImmSysOp1(op1) \| CRn(crn) \| CRm(crm) \| ImmSysOp2(op2) \| Rt(xt)); in sys()`

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