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Searched refs:CS2BCR (Results 1 – 11 of 11) sorted by relevance

/external/u-boot/arch/sh/include/asm/
Dcpu_sh7710.h25 #define CS2BCR 0xA4FD0008 macro
Dcpu_sh7785.h45 #define CS2BCR (LBSC_BASE + 0x2020) macro
Dcpu_sh7723.h37 #define CS2BCR 0xFEC10008 macro
Dcpu_sh7724.h38 #define CS2BCR 0xFEC10008 macro
Dcpu_sh7720.h62 #define CS2BCR (BSC_BASE + 0x08) macro
Dcpu_sh7780.h80 #define CS2BCR 0xFF802020 macro
Dcpu_sh7722.h127 #define CS2BCR 0xFEC10008 macro
/external/u-boot/board/mpr2/
Dmpr2.c26 __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ in board_init()
/external/u-boot/board/ms7722se/
Dlowlevel_init.S178 CS2BCR_A: .long CS2BCR ! SRAM
/external/u-boot/board/renesas/r7780mp/
Dlowlevel_init.S325 CS2BCR_A: .long CS2BCR
/external/u-boot/board/renesas/sh7785lcr/
Dlowlevel_init.S279 CS2BCR_A: .long CS2BCR