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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4  *
5  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
6  */
7 
8 #ifndef __ASM_ARCH_MX35_H
9 #define __ASM_ARCH_MX35_H
10 
11 #define ARCH_MXC
12 
13 /*
14  * IRAM
15  */
16 #define IRAM_BASE_ADDR		0x10000000	/* internal ram */
17 #define IRAM_SIZE		0x00020000	/* 128 KB */
18 
19 #define LOW_LEVEL_SRAM_STACK	0x1001E000
20 
21 /*
22  * AIPS 1
23  */
24 #define AIPS1_BASE_ADDR         0x43F00000
25 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
26 #define MAX_BASE_ADDR           0x43F04000
27 #define EVTMON_BASE_ADDR        0x43F08000
28 #define CLKCTL_BASE_ADDR        0x43F0C000
29 #define I2C1_BASE_ADDR		0x43F80000
30 #define I2C3_BASE_ADDR          0x43F84000
31 #define ATA_BASE_ADDR           0x43F8C000
32 #define UART1_BASE		0x43F90000
33 #define UART2_BASE		0x43F94000
34 #define I2C2_BASE_ADDR          0x43F98000
35 #define CSPI1_BASE_ADDR         0x43FA4000
36 #define IOMUXC_BASE_ADDR        0x43FAC000
37 
38 /*
39  * SPBA
40  */
41 #define SPBA_BASE_ADDR          0x50000000
42 #define UART3_BASE		0x5000C000
43 #define CSPI2_BASE_ADDR         0x50010000
44 #define ATA_DMA_BASE_ADDR       0x50020000
45 #define FEC_BASE_ADDR           0x50038000
46 #define SPBA_CTRL_BASE_ADDR     0x5003C000
47 
48 /*
49  * AIPS 2
50  */
51 #define AIPS2_BASE_ADDR         0x53F00000
52 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
53 #define CCM_BASE_ADDR           0x53F80000
54 #define GPT1_BASE_ADDR          0x53F90000
55 #define EPIT1_BASE_ADDR         0x53F94000
56 #define EPIT2_BASE_ADDR         0x53F98000
57 #define GPIO3_BASE_ADDR         0x53FA4000
58 #define MMC_SDHC1_BASE_ADDR	0x53FB4000
59 #define MMC_SDHC2_BASE_ADDR	0x53FB8000
60 #define MMC_SDHC3_BASE_ADDR	0x53FBC000
61 #define IPU_CTRL_BASE_ADDR	0x53FC0000
62 #define GPIO1_BASE_ADDR		0x53FCC000
63 #define GPIO2_BASE_ADDR		0x53FD0000
64 #define SDMA_BASE_ADDR		0x53FD4000
65 #define RTC_BASE_ADDR		0x53FD8000
66 #define WDOG1_BASE_ADDR		0x53FDC000
67 #define PWM_BASE_ADDR		0x53FE0000
68 #define RTIC_BASE_ADDR		0x53FEC000
69 #define IIM_BASE_ADDR		0x53FF0000
70 #define IMX_USB_BASE		0x53FF4000
71 #define IMX_USB_PORT_OFFSET	0x400
72 
73 #define IMX_CCM_BASE		CCM_BASE_ADDR
74 
75 /*
76  * ROMPATCH and AVIC
77  */
78 #define ROMPATCH_BASE_ADDR	0x60000000
79 #define AVIC_BASE_ADDR		0x68000000
80 
81 /*
82  * NAND, SDRAM, WEIM, M3IF, EMI controllers
83  */
84 #define EXT_MEM_CTRL_BASE	0xB8000000
85 #define ESDCTL_BASE_ADDR	0xB8001000
86 #define WEIM_BASE_ADDR		0xB8002000
87 #define WEIM_CTRL_CS0		WEIM_BASE_ADDR
88 #define WEIM_CTRL_CS1		(WEIM_BASE_ADDR + 0x10)
89 #define WEIM_CTRL_CS2		(WEIM_BASE_ADDR + 0x20)
90 #define WEIM_CTRL_CS3		(WEIM_BASE_ADDR + 0x30)
91 #define WEIM_CTRL_CS4		(WEIM_BASE_ADDR + 0x40)
92 #define WEIM_CTRL_CS5		(WEIM_BASE_ADDR + 0x50)
93 #define M3IF_BASE_ADDR		0xB8003000
94 #define EMI_BASE_ADDR		0xB8004000
95 
96 #define NFC_BASE_ADDR		0xBB000000
97 
98 /*
99  * Memory regions and CS
100  */
101 #define IPU_MEM_BASE_ADDR	0x70000000
102 #define CSD0_BASE_ADDR		0x80000000
103 #define CSD1_BASE_ADDR		0x90000000
104 #define CS0_BASE_ADDR		0xA0000000
105 #define CS1_BASE_ADDR		0xA8000000
106 #define CS2_BASE_ADDR		0xB0000000
107 #define CS3_BASE_ADDR		0xB2000000
108 #define CS4_BASE_ADDR		0xB4000000
109 #define CS5_BASE_ADDR		0xB6000000
110 
111 /*
112  * IRQ Controller Register Definitions.
113  */
114 #define AVIC_NIMASK		0x04
115 #define AVIC_INTTYPEH		0x18
116 #define AVIC_INTTYPEL		0x1C
117 
118 /* L210 */
119 #define L2CC_BASE_ADDR		0x30000000
120 #define L2_CACHE_LINE_SIZE		32
121 #define L2_CACHE_CTL_REG		0x100
122 #define L2_CACHE_AUX_CTL_REG		0x104
123 #define L2_CACHE_SYNC_REG		0x730
124 #define L2_CACHE_INV_LINE_REG		0x770
125 #define L2_CACHE_INV_WAY_REG		0x77C
126 #define L2_CACHE_CLEAN_LINE_REG		0x7B0
127 #define L2_CACHE_CLEAN_INV_LINE_REG	0x7F0
128 #define L2_CACHE_DBG_CTL_REG		0xF40
129 
130 #define CLKMODE_AUTO		0
131 #define CLKMODE_CONSUMER	1
132 
133 #define PLL_PD(x)		(((x) & 0xf) << 26)
134 #define PLL_MFD(x)		(((x) & 0x3ff) << 16)
135 #define PLL_MFI(x)		(((x) & 0xf) << 10)
136 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
137 
138 #define _PLL_BRM(x)	((x) << 31)
139 #define _PLL_PD(x)	(((x) - 1) << 26)
140 #define _PLL_MFD(x)	(((x) - 1) << 16)
141 #define _PLL_MFI(x)	((x) << 10)
142 #define _PLL_MFN(x)	(x)
143 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
144 	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
145 	 _PLL_MFN(mfn))
146 
147 #define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
148 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
149 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
150 
151 #define CSCR_U(x)	(WEIM_CTRL_CS#x + 0)
152 #define CSCR_L(x)	(WEIM_CTRL_CS#x + 4)
153 #define CSCR_A(x)	(WEIM_CTRL_CS#x + 8)
154 
155 #define IIM_SREV	0x24
156 #define ROMPATCH_REV	0x40
157 
158 #define IPU_CONF	IPU_CTRL_BASE_ADDR
159 
160 #define IPU_CONF_PXL_ENDIAN	(1<<8)
161 #define IPU_CONF_DU_EN		(1<<7)
162 #define IPU_CONF_DI_EN		(1<<6)
163 #define IPU_CONF_ADC_EN		(1<<5)
164 #define IPU_CONF_SDC_EN		(1<<4)
165 #define IPU_CONF_PF_EN		(1<<3)
166 #define IPU_CONF_ROT_EN		(1<<2)
167 #define IPU_CONF_IC_EN		(1<<1)
168 #define IPU_CONF_CSI_EN		(1<<0)
169 
170 /*
171  * CSPI register definitions
172  */
173 #define MXC_CSPI
174 #define MXC_CSPICTRL_EN		(1 << 0)
175 #define MXC_CSPICTRL_MODE	(1 << 1)
176 #define MXC_CSPICTRL_XCH	(1 << 2)
177 #define MXC_CSPICTRL_SMC	(1 << 3)
178 #define MXC_CSPICTRL_POL	(1 << 4)
179 #define MXC_CSPICTRL_PHA	(1 << 5)
180 #define MXC_CSPICTRL_SSCTL	(1 << 6)
181 #define MXC_CSPICTRL_SSPOL	(1 << 7)
182 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
183 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
184 #define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
185 #define MXC_CSPICTRL_TC		(1 << 7)
186 #define MXC_CSPICTRL_RXOVF	(1 << 6)
187 #define MXC_CSPICTRL_MAXBITS	0xfff
188 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
189 #define MAX_SPI_BYTES	4
190 
191 #define MXC_SPI_BASE_ADDRESSES \
192 	0x43fa4000, \
193 	0x50010000,
194 
195 #define GPIO_PORT_NUM		3
196 #define GPIO_NUM_PIN		32
197 
198 #define CHIP_REV_1_0		0x10
199 #define CHIP_REV_2_0		0x20
200 
201 #define BOARD_REV_1_0		0x0
202 #define BOARD_REV_2_0		0x1
203 
204 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
205 #include <asm/types.h>
206 
207 /* Clock Control Module (CCM) registers */
208 struct ccm_regs {
209 	u32 ccmr;	/* Control */
210 	u32 pdr0;	/* Post divider 0 */
211 	u32 pdr1;	/* Post divider 1 */
212 	u32 pdr2;	/* Post divider 2 */
213 	u32 pdr3;	/* Post divider 3 */
214 	u32 pdr4;	/* Post divider 4 */
215 	u32 rcsr;	/* CCM Status */
216 	u32 mpctl;	/* Core PLL Control */
217 	u32 ppctl;	/* Peripheral PLL Control */
218 	u32 acmr;	/* Audio clock mux */
219 	u32 cosr;	/* Clock out source */
220 	u32 cgr0;	/* Clock Gating Control 0 */
221 	u32 cgr1;	/* Clock Gating Control 1 */
222 	u32 cgr2;	/* Clock Gating Control 2 */
223 	u32 cgr3;	/* Clock Gating Control 3 */
224 	u32 reserved;
225 	u32 dcvr0;	/* DPTC Comparator 0 */
226 	u32 dcvr1;	/* DPTC Comparator 0 */
227 	u32 dcvr2;	/* DPTC Comparator 0 */
228 	u32 dcvr3;	/* DPTC Comparator 0 */
229 	u32 ltr0;	/* Load Tracking 0 */
230 	u32 ltr1;	/* Load Tracking 1 */
231 	u32 ltr2;	/* Load Tracking 2 */
232 	u32 ltr3;	/* Load Tracking 3 */
233 	u32 ltbr0;	/* Load Tracking Buffer 0 */
234 };
235 
236 /* IIM control registers */
237 struct iim_regs {
238 	u32 iim_stat;
239 	u32 iim_statm;
240 	u32 iim_err;
241 	u32 iim_emask;
242 	u32 iim_fctl;
243 	u32 iim_ua;
244 	u32 iim_la;
245 	u32 iim_sdat;
246 	u32 iim_prev;
247 	u32 iim_srev;
248 	u32 iim_prg_p;
249 	u32 iim_scs0;
250 	u32 iim_scs1;
251 	u32 iim_scs2;
252 	u32 iim_scs3;
253 	u32 res1[0x1f1];
254 	struct fuse_bank {
255 		u32 fuse_regs[0x20];
256 		u32 fuse_rsvd[0xe0];
257 	} bank[3];
258 };
259 
260 struct fuse_bank0_regs {
261 	u32 fuse0_7[8];
262 	u32 uid[8];
263 	u32 fuse16_31[0x10];
264 };
265 
266 struct fuse_bank1_regs {
267 	u32 fuse0_21[0x16];
268 	u32 usr;
269 	u32 fuse23_31[9];
270 };
271 
272 /* General Purpose Timer (GPT) registers */
273 struct gpt_regs {
274 	u32 ctrl;	/* control */
275 	u32 pre;	/* prescaler */
276 	u32 stat;	/* status */
277 	u32 intr;	/* interrupt */
278 	u32 cmp[3];	/* output compare 1-3 */
279 	u32 capt[2];	/* input capture 1-2 */
280 	u32 counter;	/* counter */
281 };
282 
283 /* CSPI registers */
284 struct cspi_regs {
285 	u32 rxdata;
286 	u32 txdata;
287 	u32 ctrl;
288 	u32 intr;
289 	u32 dma;
290 	u32 stat;
291 	u32 period;
292 	u32 test;
293 };
294 
295 struct esdc_regs {
296 	u32	esdctl0;
297 	u32	esdcfg0;
298 	u32	esdctl1;
299 	u32	esdcfg1;
300 	u32	esdmisc;
301 	u32	reserved[4];
302 	u32	esdcdly[5];
303 	u32	esdcdlyl;
304 };
305 
306 #define ESDC_MISC_RST		(1 << 1)
307 #define ESDC_MISC_MDDR_EN	(1 << 2)
308 #define ESDC_MISC_MDDR_DL_RST	(1 << 3)
309 #define ESDC_MISC_DDR_EN	(1 << 8)
310 #define ESDC_MISC_DDR2_EN	(1 << 9)
311 
312 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
313 struct max_regs {
314 	u32 mpr0;
315 	u32 pad00[3];
316 	u32 sgpcr0;
317 	u32 pad01[59];
318 	u32 mpr1;
319 	u32 pad02[3];
320 	u32 sgpcr1;
321 	u32 pad03[59];
322 	u32 mpr2;
323 	u32 pad04[3];
324 	u32 sgpcr2;
325 	u32 pad05[59];
326 	u32 mpr3;
327 	u32 pad06[3];
328 	u32 sgpcr3;
329 	u32 pad07[59];
330 	u32 mpr4;
331 	u32 pad08[3];
332 	u32 sgpcr4;
333 	u32 pad09[251];
334 	u32 mgpcr0;
335 	u32 pad10[63];
336 	u32 mgpcr1;
337 	u32 pad11[63];
338 	u32 mgpcr2;
339 	u32 pad12[63];
340 	u32 mgpcr3;
341 	u32 pad13[63];
342 	u32 mgpcr4;
343 	u32 pad14[63];
344 	u32 mgpcr5;
345 };
346 
347 /* AHB <-> IP-Bus Interface (AIPS) */
348 struct aips_regs {
349 	u32 mpr_0_7;
350 	u32 mpr_8_15;
351 	u32 pad0[6];
352 	u32 pacr_0_7;
353 	u32 pacr_8_15;
354 	u32 pacr_16_23;
355 	u32 pacr_24_31;
356 	u32 pad1[4];
357 	u32 opacr_0_7;
358 	u32 opacr_8_15;
359 	u32 opacr_16_23;
360 	u32 opacr_24_31;
361 	u32 opacr_32_39;
362 };
363 
364 /*
365  * NFMS bit in RCSR register for pagesize of nandflash
366  */
367 #define NFMS_BIT		8
368 #define NFMS_NF_DWIDTH		14
369 #define NFMS_NF_PG_SZ		8
370 
371 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
372 
373 #endif
374 
375 /*
376  * Generic timer support
377  */
378 #ifdef CONFIG_MX35_CLK32
379 #define	CONFIG_SYS_TIMER_RATE	CONFIG_MX35_CLK32
380 #else
381 #define	CONFIG_SYS_TIMER_RATE	32768
382 #endif
383 
384 #define CONFIG_SYS_TIMER_COUNTER	(GPT1_BASE_ADDR+36)
385 
386 #endif /* __ASM_ARCH_MX35_H */
387