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Searched refs:CSITE_CPU_DBG0_LAR (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-tegra/
Dap.h30 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) macro
/external/u-boot/arch/arm/mach-tegra/
Dcpu.h40 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) macro
Dcpu.c397 writel(rst, CSITE_CPU_DBG0_LAR); in clock_enable_coresight()
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dwarmboot_avp.c134 writel(reg, CSITE_CPU_DBG0_LAR); in wb_start()