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Searched refs:CS_MODE_MIPSGP64 (Results 1 – 9 of 9) sorted by relevance

/external/capstone/arch/Mips/
DMipsModule.c19 CS_MODE_MIPSGP64 | CS_MODE_BIG_ENDIAN)) in init()
DMipsDisassembler.c363 if (((mode & CS_MODE_MIPS32R6) != 0) && ((mode & CS_MODE_MIPSGP64) != 0)) { in MipsDisassembler_getInstruction()
/external/capstone/bindings/vb6/
DModule1.bas41 CS_MODE_MIPSGP64 = 128 ' General Purpose Registers are 64-bit wide (MIPS)
/external/capstone/include/
Dcapstone.h106 CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS) enumerator
/external/capstone/bindings/ocaml/
Dcapstone.ml38 | CS_MODE_MIPSGP64 (* MipsGP64 mode (MIPS architecture) *) Constructor
Docaml.c701 mode |= CS_MODE_MIPSGP64; in ocaml_cs_disasm()
832 mode |= CS_MODE_MIPSGP64; in ocaml_open()
/external/capstone/bindings/java/capstone/
DCapstone.java303 …public static final int CS_MODE_MIPSGP64 = 1 << 7; // General Purpose Registers are 64-bit wide (… field in Capstone
/external/capstone/bindings/python/capstone/
D__init__.py138 CS_MODE_MIPSGP64 = (1 << 7) # General Purpose Registers are 64-bit wide (MIPS arch) variable
/external/capstone/
DChangeLog348 MipsGP64 (CS_MODE_MIPSGP64).