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Searched refs:CTRL_BASE (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-am33xx/
Dhardware_ti814x.h22 #define CTRL_BASE 0x48140000 macro
47 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
Dhardware_am33xx.h30 #define CTRL_BASE 0x44E10000 macro
55 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
Dmux_ti814x.h29 tmp = __raw_readl(CTRL_BASE + offset); \
31 __raw_writel(tmp | value, (CTRL_BASE + offset));\
Dhardware_ti816x.h33 #define CTRL_BASE 0x48140000 macro
Dhardware_am43xx.h28 #define CTRL_BASE 0x44E10000 macro
Dmux_am43xx.h15 __raw_writel(value, (CTRL_BASE + offset));
Dmux_am33xx.h23 __raw_writel(value, (CTRL_BASE + offset));
Dmux_ti816x.h24 __raw_writel(value, (CTRL_BASE + offset));
Dcpu.h43 #define DEVICE_ID (CTRL_BASE + 0x0600)
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dsys_info.c22 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
62 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; in get_sys_clk_index()
Dclock_ti816x.c33 #define CM_PLL_BASE (CTRL_BASE + 0x0400)
73 #define CONTROL_STATUS (CTRL_BASE + 0x40)
74 #define DDR_RCD (CTRL_BASE + 0x070C)
Dprcm-regs.c13 .control_status = CTRL_BASE + 0x40,
Dclock_ti814x.c104 #define SATA_PLL_BASE (CTRL_BASE + 0x0720)
/external/u-boot/board/ti/am43xx/
Dboard.c348 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; in get_opp_offset()