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Searched refs:CTX_PHY_REG (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_debug.c627 CTX_PHY_REG(csindex), in ddr3_tip_print_stability_log()
1336 reg = (direction == 0) ? CTX_PHY_REG(cs) : CRX_PHY_REG(cs); in ddr3_tip_run_sweep_test()
1501 CTX_PHY_REG(cs), MASK_ALL_BITS); in ddr3_tip_run_leveling_sweep_test()
1545 CTX_PHY_REG(cs), in ddr3_tip_run_leveling_sweep_test()
1596 CTX_PHY_REG(cs), in ddr3_tip_run_leveling_sweep_test()
1634 ddr3_tip_write_adll_value(dev_num, ctrl_adll1, CTX_PHY_REG(cs)); in ddr3_tip_run_leveling_sweep_test()
Dddr3_training_bist.c502 ddr3_tip_read_adll_value(0, wr_ctrl_adll, CTX_PHY_REG(cs), MASK_ALL_BITS); in mv_ddr_dm_vw_get()
545 DDR_PHY_DATA, CTX_PHY_REG(cs), adll_tap); in mv_ddr_dm_vw_get()
575 subphy, DDR_PHY_DATA, CTX_PHY_REG(cs), in mv_ddr_dm_vw_get()
Dddr3_training_leveling.c1218 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1238 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1243 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1264 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
1269 CTX_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling_supp()
Dmv_ddr_regs.h396 #define CTX_PHY_REG(cs) (CTX_PHY_BASE + (cs) * 0x4) macro
Dddr3_training_ip_engine.c473 reg_data = CTX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
1471 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1493 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
Dddr3_training_pbs.c71 CTX_PHY_REG(effective_cs); in ddr3_tip_pbs()
852 CTX_PHY_REG(effective_cs); in ddr3_tip_pbs()
Dddr3_training_centralization.c93 reg_phy_off = CTX_PHY_REG(effective_cs); in ddr3_tip_centralization()
Dddr3_training.c2033 CTX_PHY_REG(effective_cs), phy_reg1_val)); in ddr3_tip_ddr3_reset_phy_regs()
2119 CTX_PHY_REG(effective_cs), reg_val1)); in ddr3_tip_adll_regs_bypass()