Searched refs:CVT_D_W (Results 1 – 10 of 10) sorted by relevance
/external/v8/src/compiler/mips/ |
D | instruction-scheduler-mips.cc | 345 CVT_D_W = 4, enumerator 682 Mthc1Latency() + Latency::CVT_D_W + Latency::BRANCH + in CvtDUwLatency() 683 Latency::ADD_D + Latency::CVT_D_W; in CvtDUwLatency() 1713 return Latency::CVT_D_W; in GetInstructionLatency()
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/external/v8/src/compiler/mips64/ |
D | instruction-scheduler-mips64.cc | 378 CVT_D_W = 4, enumerator 1488 return Latency::MTC1 + Latency::CVT_D_W; in GetInstructionLatency()
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/external/v8/src/mips/ |
D | constants-mips.h | 666 CVT_D_W = ((4U << 3) + 1), enumerator
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D | disasm-mips.cc | 1246 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()
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D | assembler-mips.cc | 3129 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W); in cvt_d_w()
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D | simulator-mips.cc | 3074 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()
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/external/v8/src/mips64/ |
D | constants-mips64.h | 696 CVT_D_W = ((4U << 3) + 1), enumerator
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D | disasm-mips64.cc | 1319 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()
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D | assembler-mips64.cc | 3446 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W); in cvt_d_w()
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D | simulator-mips64.cc | 3367 case CVT_D_W: // Convert word to double. in DecodeTypeRegisterWRsType()
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