| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 376 CVT_S_W = 4, enumerator
1045 Latency::MFC1 + Latency::BRANCH + Latency::CVT_S_W + 2 + in Float32RoundLatency()
1490 return Latency::MTC1 + Latency::CVT_S_W; in GetInstructionLatency()
|
| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 343 CVT_S_W = 4, enumerator
673 Latency::MFC1 + Latency::BRANCH + Latency::CVT_S_W; in Float32RoundLatency()
1715 return Latency::CVT_S_W; in GetInstructionLatency()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/Mips/ |
| D | live-debug-values-reg-copy.mir | 191 $f0 = CVT_S_W killed $f0, debug-location !19
227 $f0 = CVT_S_W killed $f0, debug-location !19
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 139 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
366 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 67 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 369 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
|
| D | MipsInstrFPU.td | 308 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 665 CVT_S_W = ((4U << 3) + 0), enumerator
|
| D | disasm-mips.cc | 1243 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
|
| D | assembler-mips.cc | 3112 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); in cvt_s_w()
|
| D | simulator-mips.cc | 3070 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 101 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 101 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 101 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 695 CVT_S_W = ((4U << 3) + 0), enumerator
|
| D | disasm-mips64.cc | 1316 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
|
| D | assembler-mips64.cc | 3430 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); in cvt_s_w()
|
| D | simulator-mips64.cc | 3363 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 99 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 447 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
|
| D | MipsInstrFPU.td | 419 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 99 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 101 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 481 24365U, // CVT_S_W
2195 0U, // CVT_S_W
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1064 UINT64_C(1182793760), // CVT_S_W
3158 case Mips::CVT_S_W:
8790 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_S_W = 1051
|