Searched refs:CYCLES (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/LLVM/tools/llvm-config/ |
| D | find-cycles.pl | 26 my @CYCLES;
44 foreach my $cycle (@CYCLES) {
90 my %CYCLES;
102 unless (defined $CYCLES{$module}) {
104 $CYCLES{$module} = \%cycle;
112 foreach my $cycle (values %CYCLES) {
115 push @CYCLES, $cycle;
147 if (defined $CYCLES{$item}) {
150 foreach my $old_item (keys %{$CYCLES{$item}}) {
159 $CYCLES{$item} = $cycle_ref;
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| /external/ltp/testcases/cve/ |
| D | meltdown.c | 180 #define CYCLES 10000 macro
189 for (i = 0; i < CYCLES; i++) { in readbit()
205 if (hist[1] > CYCLES / 10) in readbit()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinRegisterInfo.td | 186 def CYCLES : Ri<6, 6, "cycles">;
247 LC0, LT0, LB0, LC1, LT1, LB1, CYCLES, CYCLES2,
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| D | BlackfinRegisterInfo.cpp | 69 Reserved.set(CYCLES).set(CYCLES2); in getReservedRegs()
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| D | README.txt | 109 We have CYCLES and CYCLES2 registers, but the readcyclecounter intrinsic wants
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| D | BlackfinISelLowering.cpp | 490 SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32); in ReplaceNodeResults()
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| /external/python/cpython2/Lib/plat-unixware7/ |
| D | IN.py | 440 def CYCLES_SINCE(c): return CYCLES_BETWEEN((c), CYCLES())
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