1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-12-19 18:19:46)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2018-01-03 15:58:51)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-12-19 18:19:46)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 146261 bytes, from 2018-01-03 15:58:51)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
20
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46
47 enum a4xx_color_fmt {
48 RB4_A8_UNORM = 1,
49 RB4_R8_UNORM = 2,
50 RB4_R8_SNORM = 3,
51 RB4_R8_UINT = 4,
52 RB4_R8_SINT = 5,
53 RB4_R4G4B4A4_UNORM = 8,
54 RB4_R5G5B5A1_UNORM = 10,
55 RB4_R5G6B5_UNORM = 14,
56 RB4_R8G8_UNORM = 15,
57 RB4_R8G8_SNORM = 16,
58 RB4_R8G8_UINT = 17,
59 RB4_R8G8_SINT = 18,
60 RB4_R16_UNORM = 19,
61 RB4_R16_SNORM = 20,
62 RB4_R16_FLOAT = 21,
63 RB4_R16_UINT = 22,
64 RB4_R16_SINT = 23,
65 RB4_R8G8B8_UNORM = 25,
66 RB4_R8G8B8A8_UNORM = 26,
67 RB4_R8G8B8A8_SNORM = 28,
68 RB4_R8G8B8A8_UINT = 29,
69 RB4_R8G8B8A8_SINT = 30,
70 RB4_R10G10B10A2_UNORM = 31,
71 RB4_R10G10B10A2_UINT = 34,
72 RB4_R11G11B10_FLOAT = 39,
73 RB4_R16G16_UNORM = 40,
74 RB4_R16G16_SNORM = 41,
75 RB4_R16G16_FLOAT = 42,
76 RB4_R16G16_UINT = 43,
77 RB4_R16G16_SINT = 44,
78 RB4_R32_FLOAT = 45,
79 RB4_R32_UINT = 46,
80 RB4_R32_SINT = 47,
81 RB4_R16G16B16A16_UNORM = 52,
82 RB4_R16G16B16A16_SNORM = 53,
83 RB4_R16G16B16A16_FLOAT = 54,
84 RB4_R16G16B16A16_UINT = 55,
85 RB4_R16G16B16A16_SINT = 56,
86 RB4_R32G32_FLOAT = 57,
87 RB4_R32G32_UINT = 58,
88 RB4_R32G32_SINT = 59,
89 RB4_R32G32B32A32_FLOAT = 60,
90 RB4_R32G32B32A32_UINT = 61,
91 RB4_R32G32B32A32_SINT = 62,
92 };
93
94 enum a4xx_tile_mode {
95 TILE4_LINEAR = 0,
96 TILE4_2 = 2,
97 TILE4_3 = 3,
98 };
99
100 enum a4xx_vtx_fmt {
101 VFMT4_32_FLOAT = 1,
102 VFMT4_32_32_FLOAT = 2,
103 VFMT4_32_32_32_FLOAT = 3,
104 VFMT4_32_32_32_32_FLOAT = 4,
105 VFMT4_16_FLOAT = 5,
106 VFMT4_16_16_FLOAT = 6,
107 VFMT4_16_16_16_FLOAT = 7,
108 VFMT4_16_16_16_16_FLOAT = 8,
109 VFMT4_32_FIXED = 9,
110 VFMT4_32_32_FIXED = 10,
111 VFMT4_32_32_32_FIXED = 11,
112 VFMT4_32_32_32_32_FIXED = 12,
113 VFMT4_11_11_10_FLOAT = 13,
114 VFMT4_16_SINT = 16,
115 VFMT4_16_16_SINT = 17,
116 VFMT4_16_16_16_SINT = 18,
117 VFMT4_16_16_16_16_SINT = 19,
118 VFMT4_16_UINT = 20,
119 VFMT4_16_16_UINT = 21,
120 VFMT4_16_16_16_UINT = 22,
121 VFMT4_16_16_16_16_UINT = 23,
122 VFMT4_16_SNORM = 24,
123 VFMT4_16_16_SNORM = 25,
124 VFMT4_16_16_16_SNORM = 26,
125 VFMT4_16_16_16_16_SNORM = 27,
126 VFMT4_16_UNORM = 28,
127 VFMT4_16_16_UNORM = 29,
128 VFMT4_16_16_16_UNORM = 30,
129 VFMT4_16_16_16_16_UNORM = 31,
130 VFMT4_32_UINT = 32,
131 VFMT4_32_32_UINT = 33,
132 VFMT4_32_32_32_UINT = 34,
133 VFMT4_32_32_32_32_UINT = 35,
134 VFMT4_32_SINT = 36,
135 VFMT4_32_32_SINT = 37,
136 VFMT4_32_32_32_SINT = 38,
137 VFMT4_32_32_32_32_SINT = 39,
138 VFMT4_8_UINT = 40,
139 VFMT4_8_8_UINT = 41,
140 VFMT4_8_8_8_UINT = 42,
141 VFMT4_8_8_8_8_UINT = 43,
142 VFMT4_8_UNORM = 44,
143 VFMT4_8_8_UNORM = 45,
144 VFMT4_8_8_8_UNORM = 46,
145 VFMT4_8_8_8_8_UNORM = 47,
146 VFMT4_8_SINT = 48,
147 VFMT4_8_8_SINT = 49,
148 VFMT4_8_8_8_SINT = 50,
149 VFMT4_8_8_8_8_SINT = 51,
150 VFMT4_8_SNORM = 52,
151 VFMT4_8_8_SNORM = 53,
152 VFMT4_8_8_8_SNORM = 54,
153 VFMT4_8_8_8_8_SNORM = 55,
154 VFMT4_10_10_10_2_UINT = 56,
155 VFMT4_10_10_10_2_UNORM = 57,
156 VFMT4_10_10_10_2_SINT = 58,
157 VFMT4_10_10_10_2_SNORM = 59,
158 VFMT4_2_10_10_10_UINT = 60,
159 VFMT4_2_10_10_10_UNORM = 61,
160 VFMT4_2_10_10_10_SINT = 62,
161 VFMT4_2_10_10_10_SNORM = 63,
162 };
163
164 enum a4xx_tex_fmt {
165 TFMT4_A8_UNORM = 3,
166 TFMT4_8_UNORM = 4,
167 TFMT4_8_SNORM = 5,
168 TFMT4_8_UINT = 6,
169 TFMT4_8_SINT = 7,
170 TFMT4_4_4_4_4_UNORM = 8,
171 TFMT4_5_5_5_1_UNORM = 9,
172 TFMT4_5_6_5_UNORM = 11,
173 TFMT4_L8_A8_UNORM = 13,
174 TFMT4_8_8_UNORM = 14,
175 TFMT4_8_8_SNORM = 15,
176 TFMT4_8_8_UINT = 16,
177 TFMT4_8_8_SINT = 17,
178 TFMT4_16_UNORM = 18,
179 TFMT4_16_SNORM = 19,
180 TFMT4_16_FLOAT = 20,
181 TFMT4_16_UINT = 21,
182 TFMT4_16_SINT = 22,
183 TFMT4_8_8_8_8_UNORM = 28,
184 TFMT4_8_8_8_8_SNORM = 29,
185 TFMT4_8_8_8_8_UINT = 30,
186 TFMT4_8_8_8_8_SINT = 31,
187 TFMT4_9_9_9_E5_FLOAT = 32,
188 TFMT4_10_10_10_2_UNORM = 33,
189 TFMT4_10_10_10_2_UINT = 34,
190 TFMT4_11_11_10_FLOAT = 37,
191 TFMT4_16_16_UNORM = 38,
192 TFMT4_16_16_SNORM = 39,
193 TFMT4_16_16_FLOAT = 40,
194 TFMT4_16_16_UINT = 41,
195 TFMT4_16_16_SINT = 42,
196 TFMT4_32_FLOAT = 43,
197 TFMT4_32_UINT = 44,
198 TFMT4_32_SINT = 45,
199 TFMT4_16_16_16_16_UNORM = 51,
200 TFMT4_16_16_16_16_SNORM = 52,
201 TFMT4_16_16_16_16_FLOAT = 53,
202 TFMT4_16_16_16_16_UINT = 54,
203 TFMT4_16_16_16_16_SINT = 55,
204 TFMT4_32_32_FLOAT = 56,
205 TFMT4_32_32_UINT = 57,
206 TFMT4_32_32_SINT = 58,
207 TFMT4_32_32_32_FLOAT = 59,
208 TFMT4_32_32_32_UINT = 60,
209 TFMT4_32_32_32_SINT = 61,
210 TFMT4_32_32_32_32_FLOAT = 63,
211 TFMT4_32_32_32_32_UINT = 64,
212 TFMT4_32_32_32_32_SINT = 65,
213 TFMT4_X8Z24_UNORM = 71,
214 TFMT4_DXT1 = 86,
215 TFMT4_DXT3 = 87,
216 TFMT4_DXT5 = 88,
217 TFMT4_RGTC1_UNORM = 90,
218 TFMT4_RGTC1_SNORM = 91,
219 TFMT4_RGTC2_UNORM = 94,
220 TFMT4_RGTC2_SNORM = 95,
221 TFMT4_BPTC_UFLOAT = 97,
222 TFMT4_BPTC_FLOAT = 98,
223 TFMT4_BPTC = 99,
224 TFMT4_ATC_RGB = 100,
225 TFMT4_ATC_RGBA_EXPLICIT = 101,
226 TFMT4_ATC_RGBA_INTERPOLATED = 102,
227 TFMT4_ETC2_RG11_UNORM = 103,
228 TFMT4_ETC2_RG11_SNORM = 104,
229 TFMT4_ETC2_R11_UNORM = 105,
230 TFMT4_ETC2_R11_SNORM = 106,
231 TFMT4_ETC1 = 107,
232 TFMT4_ETC2_RGB8 = 108,
233 TFMT4_ETC2_RGBA8 = 109,
234 TFMT4_ETC2_RGB8A1 = 110,
235 TFMT4_ASTC_4x4 = 111,
236 TFMT4_ASTC_5x4 = 112,
237 TFMT4_ASTC_5x5 = 113,
238 TFMT4_ASTC_6x5 = 114,
239 TFMT4_ASTC_6x6 = 115,
240 TFMT4_ASTC_8x5 = 116,
241 TFMT4_ASTC_8x6 = 117,
242 TFMT4_ASTC_8x8 = 118,
243 TFMT4_ASTC_10x5 = 119,
244 TFMT4_ASTC_10x6 = 120,
245 TFMT4_ASTC_10x8 = 121,
246 TFMT4_ASTC_10x10 = 122,
247 TFMT4_ASTC_12x10 = 123,
248 TFMT4_ASTC_12x12 = 124,
249 };
250
251 enum a4xx_tex_fetchsize {
252 TFETCH4_1_BYTE = 0,
253 TFETCH4_2_BYTE = 1,
254 TFETCH4_4_BYTE = 2,
255 TFETCH4_8_BYTE = 3,
256 TFETCH4_16_BYTE = 4,
257 };
258
259 enum a4xx_depth_format {
260 DEPTH4_NONE = 0,
261 DEPTH4_16 = 1,
262 DEPTH4_24_8 = 2,
263 DEPTH4_32 = 3,
264 };
265
266 enum a4xx_ccu_perfcounter_select {
267 CCU_BUSY_CYCLES = 0,
268 CCU_RB_DEPTH_RETURN_STALL = 2,
269 CCU_RB_COLOR_RETURN_STALL = 3,
270 CCU_DEPTH_BLOCKS = 6,
271 CCU_COLOR_BLOCKS = 7,
272 CCU_DEPTH_BLOCK_HIT = 8,
273 CCU_COLOR_BLOCK_HIT = 9,
274 CCU_DEPTH_FLAG1_COUNT = 10,
275 CCU_DEPTH_FLAG2_COUNT = 11,
276 CCU_DEPTH_FLAG3_COUNT = 12,
277 CCU_DEPTH_FLAG4_COUNT = 13,
278 CCU_COLOR_FLAG1_COUNT = 14,
279 CCU_COLOR_FLAG2_COUNT = 15,
280 CCU_COLOR_FLAG3_COUNT = 16,
281 CCU_COLOR_FLAG4_COUNT = 17,
282 CCU_PARTIAL_BLOCK_READ = 18,
283 };
284
285 enum a4xx_cp_perfcounter_select {
286 CP_ALWAYS_COUNT = 0,
287 CP_BUSY = 1,
288 CP_PFP_IDLE = 2,
289 CP_PFP_BUSY_WORKING = 3,
290 CP_PFP_STALL_CYCLES_ANY = 4,
291 CP_PFP_STARVE_CYCLES_ANY = 5,
292 CP_PFP_STARVED_PER_LOAD_ADDR = 6,
293 CP_PFP_STALLED_PER_STORE_ADDR = 7,
294 CP_PFP_PC_PROFILE = 8,
295 CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
296 CP_PFP_COND_INDIRECT_DISCARDED = 10,
297 CP_LONG_RESUMPTIONS = 11,
298 CP_RESUME_CYCLES = 12,
299 CP_RESUME_TO_BOUNDARY_CYCLES = 13,
300 CP_LONG_PREEMPTIONS = 14,
301 CP_PREEMPT_CYCLES = 15,
302 CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
303 CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
304 CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
305 CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
306 CP_ME_FIFO_FULL_ME_BUSY = 20,
307 CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
308 CP_ME_WAITING_FOR_PACKETS = 22,
309 CP_ME_BUSY_WORKING = 23,
310 CP_ME_STARVE_CYCLES_ANY = 24,
311 CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
312 CP_ME_STALL_CYCLES_PER_PROFILE = 26,
313 CP_ME_PC_PROFILE = 27,
314 CP_RCIU_FIFO_EMPTY = 28,
315 CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
316 CP_RCIU_FIFO_FULL = 30,
317 CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
318 CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
319 CP_RCIU_FIFO_FULL_OTHER = 33,
320 CP_AHB_IDLE = 34,
321 CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
322 CP_AHB_STALL_ON_GRANT_SPLIT = 36,
323 CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
324 CP_AHB_BUSY_WORKING = 38,
325 CP_AHB_BUSY_STALL_ON_HRDY = 39,
326 CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
327 };
328
329 enum a4xx_gras_ras_perfcounter_select {
330 RAS_SUPER_TILES = 0,
331 RAS_8X8_TILES = 1,
332 RAS_4X4_TILES = 2,
333 RAS_BUSY_CYCLES = 3,
334 RAS_STALL_CYCLES_BY_RB = 4,
335 RAS_STALL_CYCLES_BY_VSC = 5,
336 RAS_STARVE_CYCLES_BY_TSE = 6,
337 RAS_SUPERTILE_CYCLES = 7,
338 RAS_TILE_CYCLES = 8,
339 RAS_FULLY_COVERED_SUPER_TILES = 9,
340 RAS_FULLY_COVERED_8X8_TILES = 10,
341 RAS_4X4_PRIM = 11,
342 RAS_8X4_4X8_PRIM = 12,
343 RAS_8X8_PRIM = 13,
344 };
345
346 enum a4xx_gras_tse_perfcounter_select {
347 TSE_INPUT_PRIM = 0,
348 TSE_INPUT_NULL_PRIM = 1,
349 TSE_TRIVAL_REJ_PRIM = 2,
350 TSE_CLIPPED_PRIM = 3,
351 TSE_NEW_PRIM = 4,
352 TSE_ZERO_AREA_PRIM = 5,
353 TSE_FACENESS_CULLED_PRIM = 6,
354 TSE_ZERO_PIXEL_PRIM = 7,
355 TSE_OUTPUT_NULL_PRIM = 8,
356 TSE_OUTPUT_VISIBLE_PRIM = 9,
357 TSE_PRE_CLIP_PRIM = 10,
358 TSE_POST_CLIP_PRIM = 11,
359 TSE_BUSY_CYCLES = 12,
360 TSE_PC_STARVE = 13,
361 TSE_RAS_STALL = 14,
362 TSE_STALL_BARYPLANE_FIFO_FULL = 15,
363 TSE_STALL_ZPLANE_FIFO_FULL = 16,
364 };
365
366 enum a4xx_hlsq_perfcounter_select {
367 HLSQ_SP_VS_STAGE_CONSTANT = 0,
368 HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
369 HLSQ_SP_FS_STAGE_CONSTANT = 2,
370 HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
371 HLSQ_TP_STATE = 4,
372 HLSQ_QUADS = 5,
373 HLSQ_PIXELS = 6,
374 HLSQ_VERTICES = 7,
375 HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
376 HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
377 HLSQ_BUSY_CYCLES = 15,
378 HLSQ_STALL_CYCLES_SP_STATE = 16,
379 HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
380 HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
381 HLSQ_STALL_CYCLES_UCHE = 19,
382 HLSQ_RBBM_LOAD_CYCLES = 20,
383 HLSQ_DI_TO_VS_START_SP = 21,
384 HLSQ_DI_TO_FS_START_SP = 22,
385 HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
386 HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
387 HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
388 HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
389 HLSQ_UCHE_LATENCY_CYCLES = 27,
390 HLSQ_UCHE_LATENCY_COUNT = 28,
391 HLSQ_STARVE_CYCLES_VFD = 29,
392 };
393
394 enum a4xx_pc_perfcounter_select {
395 PC_VIS_STREAMS_LOADED = 0,
396 PC_VPC_PRIMITIVES = 2,
397 PC_DEAD_PRIM = 3,
398 PC_LIVE_PRIM = 4,
399 PC_DEAD_DRAWCALLS = 5,
400 PC_LIVE_DRAWCALLS = 6,
401 PC_VERTEX_MISSES = 7,
402 PC_STALL_CYCLES_VFD = 9,
403 PC_STALL_CYCLES_TSE = 10,
404 PC_STALL_CYCLES_UCHE = 11,
405 PC_WORKING_CYCLES = 12,
406 PC_IA_VERTICES = 13,
407 PC_GS_PRIMITIVES = 14,
408 PC_HS_INVOCATIONS = 15,
409 PC_DS_INVOCATIONS = 16,
410 PC_DS_PRIMITIVES = 17,
411 PC_STARVE_CYCLES_FOR_INDEX = 20,
412 PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
413 PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
414 PC_STALL_CYCLES_TESS = 23,
415 PC_STARVE_CYCLES_FOR_POSITION = 24,
416 PC_MODE0_DRAWCALL = 25,
417 PC_MODE1_DRAWCALL = 26,
418 PC_MODE2_DRAWCALL = 27,
419 PC_MODE3_DRAWCALL = 28,
420 PC_MODE4_DRAWCALL = 29,
421 PC_PREDICATED_DEAD_DRAWCALL = 30,
422 PC_STALL_CYCLES_BY_TSE_ONLY = 31,
423 PC_STALL_CYCLES_BY_VPC_ONLY = 32,
424 PC_VPC_POS_DATA_TRANSACTION = 33,
425 PC_BUSY_CYCLES = 34,
426 PC_STARVE_CYCLES_DI = 35,
427 PC_STALL_CYCLES_VPC = 36,
428 TESS_WORKING_CYCLES = 37,
429 TESS_NUM_CYCLES_SETUP_WORKING = 38,
430 TESS_NUM_CYCLES_PTGEN_WORKING = 39,
431 TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
432 TESS_BUSY_CYCLES = 41,
433 TESS_STARVE_CYCLES_PC = 42,
434 TESS_STALL_CYCLES_PC = 43,
435 };
436
437 enum a4xx_pwr_perfcounter_select {
438 PWR_CORE_CLOCK_CYCLES = 0,
439 PWR_BUSY_CLOCK_CYCLES = 1,
440 };
441
442 enum a4xx_rb_perfcounter_select {
443 RB_BUSY_CYCLES = 0,
444 RB_BUSY_CYCLES_BINNING = 1,
445 RB_BUSY_CYCLES_RENDERING = 2,
446 RB_BUSY_CYCLES_RESOLVE = 3,
447 RB_STARVE_CYCLES_BY_SP = 4,
448 RB_STARVE_CYCLES_BY_RAS = 5,
449 RB_STARVE_CYCLES_BY_MARB = 6,
450 RB_STALL_CYCLES_BY_MARB = 7,
451 RB_STALL_CYCLES_BY_HLSQ = 8,
452 RB_RB_RB_MARB_DATA = 9,
453 RB_SP_RB_QUAD = 10,
454 RB_RAS_RB_Z_QUADS = 11,
455 RB_GMEM_CH0_READ = 12,
456 RB_GMEM_CH1_READ = 13,
457 RB_GMEM_CH0_WRITE = 14,
458 RB_GMEM_CH1_WRITE = 15,
459 RB_CP_CONTEXT_DONE = 16,
460 RB_CP_CACHE_FLUSH = 17,
461 RB_CP_ZPASS_DONE = 18,
462 RB_STALL_FIFO0_FULL = 19,
463 RB_STALL_FIFO1_FULL = 20,
464 RB_STALL_FIFO2_FULL = 21,
465 RB_STALL_FIFO3_FULL = 22,
466 RB_RB_HLSQ_TRANSACTIONS = 23,
467 RB_Z_READ = 24,
468 RB_Z_WRITE = 25,
469 RB_C_READ = 26,
470 RB_C_WRITE = 27,
471 RB_C_READ_LATENCY = 28,
472 RB_Z_READ_LATENCY = 29,
473 RB_STALL_BY_UCHE = 30,
474 RB_MARB_UCHE_TRANSACTIONS = 31,
475 RB_CACHE_STALL_MISS = 32,
476 RB_CACHE_STALL_FIFO_FULL = 33,
477 RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
478 RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
479 RB_SAMPLER_UNITS_ACTIVE = 36,
480 RB_TOTAL_PASS = 38,
481 RB_Z_PASS = 39,
482 RB_Z_FAIL = 40,
483 RB_S_FAIL = 41,
484 RB_POWER0 = 42,
485 RB_POWER1 = 43,
486 RB_POWER2 = 44,
487 RB_POWER3 = 45,
488 RB_POWER4 = 46,
489 RB_POWER5 = 47,
490 RB_POWER6 = 48,
491 RB_POWER7 = 49,
492 };
493
494 enum a4xx_rbbm_perfcounter_select {
495 RBBM_ALWAYS_ON = 0,
496 RBBM_VBIF_BUSY = 1,
497 RBBM_TSE_BUSY = 2,
498 RBBM_RAS_BUSY = 3,
499 RBBM_PC_DCALL_BUSY = 4,
500 RBBM_PC_VSD_BUSY = 5,
501 RBBM_VFD_BUSY = 6,
502 RBBM_VPC_BUSY = 7,
503 RBBM_UCHE_BUSY = 8,
504 RBBM_VSC_BUSY = 9,
505 RBBM_HLSQ_BUSY = 10,
506 RBBM_ANY_RB_BUSY = 11,
507 RBBM_ANY_TPL1_BUSY = 12,
508 RBBM_ANY_SP_BUSY = 13,
509 RBBM_ANY_MARB_BUSY = 14,
510 RBBM_ANY_ARB_BUSY = 15,
511 RBBM_AHB_STATUS_BUSY = 16,
512 RBBM_AHB_STATUS_STALLED = 17,
513 RBBM_AHB_STATUS_TXFR = 18,
514 RBBM_AHB_STATUS_TXFR_SPLIT = 19,
515 RBBM_AHB_STATUS_TXFR_ERROR = 20,
516 RBBM_AHB_STATUS_LONG_STALL = 21,
517 RBBM_STATUS_MASKED = 22,
518 RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
519 RBBM_TESS_BUSY = 24,
520 RBBM_COM_BUSY = 25,
521 RBBM_DCOM_BUSY = 32,
522 RBBM_ANY_CCU_BUSY = 33,
523 RBBM_DPM_BUSY = 34,
524 };
525
526 enum a4xx_sp_perfcounter_select {
527 SP_LM_LOAD_INSTRUCTIONS = 0,
528 SP_LM_STORE_INSTRUCTIONS = 1,
529 SP_LM_ATOMICS = 2,
530 SP_GM_LOAD_INSTRUCTIONS = 3,
531 SP_GM_STORE_INSTRUCTIONS = 4,
532 SP_GM_ATOMICS = 5,
533 SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
534 SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
535 SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
536 SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
537 SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
538 SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
539 SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
540 SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
541 SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
542 SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
543 SP_VS_INSTRUCTIONS = 17,
544 SP_FS_INSTRUCTIONS = 18,
545 SP_ADDR_LOCK_COUNT = 19,
546 SP_UCHE_READ_TRANS = 20,
547 SP_UCHE_WRITE_TRANS = 21,
548 SP_EXPORT_VPC_TRANS = 22,
549 SP_EXPORT_RB_TRANS = 23,
550 SP_PIXELS_KILLED = 24,
551 SP_ICL1_REQUESTS = 25,
552 SP_ICL1_MISSES = 26,
553 SP_ICL0_REQUESTS = 27,
554 SP_ICL0_MISSES = 28,
555 SP_ALU_WORKING_CYCLES = 29,
556 SP_EFU_WORKING_CYCLES = 30,
557 SP_STALL_CYCLES_BY_VPC = 31,
558 SP_STALL_CYCLES_BY_TP = 32,
559 SP_STALL_CYCLES_BY_UCHE = 33,
560 SP_STALL_CYCLES_BY_RB = 34,
561 SP_BUSY_CYCLES = 35,
562 SP_HS_INSTRUCTIONS = 36,
563 SP_DS_INSTRUCTIONS = 37,
564 SP_GS_INSTRUCTIONS = 38,
565 SP_CS_INSTRUCTIONS = 39,
566 SP_SCHEDULER_NON_WORKING = 40,
567 SP_WAVE_CONTEXTS = 41,
568 SP_WAVE_CONTEXT_CYCLES = 42,
569 SP_POWER0 = 43,
570 SP_POWER1 = 44,
571 SP_POWER2 = 45,
572 SP_POWER3 = 46,
573 SP_POWER4 = 47,
574 SP_POWER5 = 48,
575 SP_POWER6 = 49,
576 SP_POWER7 = 50,
577 SP_POWER8 = 51,
578 SP_POWER9 = 52,
579 SP_POWER10 = 53,
580 SP_POWER11 = 54,
581 SP_POWER12 = 55,
582 SP_POWER13 = 56,
583 SP_POWER14 = 57,
584 SP_POWER15 = 58,
585 };
586
587 enum a4xx_tp_perfcounter_select {
588 TP_L1_REQUESTS = 0,
589 TP_L1_MISSES = 1,
590 TP_QUADS_OFFSET = 8,
591 TP_QUAD_SHADOW = 9,
592 TP_QUADS_ARRAY = 10,
593 TP_QUADS_GRADIENT = 11,
594 TP_QUADS_1D2D = 12,
595 TP_QUADS_3DCUBE = 13,
596 TP_BUSY_CYCLES = 16,
597 TP_STALL_CYCLES_BY_ARB = 17,
598 TP_STATE_CACHE_REQUESTS = 20,
599 TP_STATE_CACHE_MISSES = 21,
600 TP_POWER0 = 22,
601 TP_POWER1 = 23,
602 TP_POWER2 = 24,
603 TP_POWER3 = 25,
604 TP_POWER4 = 26,
605 TP_POWER5 = 27,
606 TP_POWER6 = 28,
607 TP_POWER7 = 29,
608 };
609
610 enum a4xx_uche_perfcounter_select {
611 UCHE_VBIF_READ_BEATS_TP = 0,
612 UCHE_VBIF_READ_BEATS_VFD = 1,
613 UCHE_VBIF_READ_BEATS_HLSQ = 2,
614 UCHE_VBIF_READ_BEATS_MARB = 3,
615 UCHE_VBIF_READ_BEATS_SP = 4,
616 UCHE_READ_REQUESTS_TP = 5,
617 UCHE_READ_REQUESTS_VFD = 6,
618 UCHE_READ_REQUESTS_HLSQ = 7,
619 UCHE_READ_REQUESTS_MARB = 8,
620 UCHE_READ_REQUESTS_SP = 9,
621 UCHE_WRITE_REQUESTS_MARB = 10,
622 UCHE_WRITE_REQUESTS_SP = 11,
623 UCHE_TAG_CHECK_FAILS = 12,
624 UCHE_EVICTS = 13,
625 UCHE_FLUSHES = 14,
626 UCHE_VBIF_LATENCY_CYCLES = 15,
627 UCHE_VBIF_LATENCY_SAMPLES = 16,
628 UCHE_BUSY_CYCLES = 17,
629 UCHE_VBIF_READ_BEATS_PC = 18,
630 UCHE_READ_REQUESTS_PC = 19,
631 UCHE_WRITE_REQUESTS_VPC = 20,
632 UCHE_STALL_BY_VBIF = 21,
633 UCHE_WRITE_REQUESTS_VSC = 22,
634 UCHE_POWER0 = 23,
635 UCHE_POWER1 = 24,
636 UCHE_POWER2 = 25,
637 UCHE_POWER3 = 26,
638 UCHE_POWER4 = 27,
639 UCHE_POWER5 = 28,
640 UCHE_POWER6 = 29,
641 UCHE_POWER7 = 30,
642 };
643
644 enum a4xx_vbif_perfcounter_select {
645 AXI_READ_REQUESTS_ID_0 = 0,
646 AXI_READ_REQUESTS_ID_1 = 1,
647 AXI_READ_REQUESTS_ID_2 = 2,
648 AXI_READ_REQUESTS_ID_3 = 3,
649 AXI_READ_REQUESTS_ID_4 = 4,
650 AXI_READ_REQUESTS_ID_5 = 5,
651 AXI_READ_REQUESTS_ID_6 = 6,
652 AXI_READ_REQUESTS_ID_7 = 7,
653 AXI_READ_REQUESTS_ID_8 = 8,
654 AXI_READ_REQUESTS_ID_9 = 9,
655 AXI_READ_REQUESTS_ID_10 = 10,
656 AXI_READ_REQUESTS_ID_11 = 11,
657 AXI_READ_REQUESTS_ID_12 = 12,
658 AXI_READ_REQUESTS_ID_13 = 13,
659 AXI_READ_REQUESTS_ID_14 = 14,
660 AXI_READ_REQUESTS_ID_15 = 15,
661 AXI0_READ_REQUESTS_TOTAL = 16,
662 AXI1_READ_REQUESTS_TOTAL = 17,
663 AXI2_READ_REQUESTS_TOTAL = 18,
664 AXI3_READ_REQUESTS_TOTAL = 19,
665 AXI_READ_REQUESTS_TOTAL = 20,
666 AXI_WRITE_REQUESTS_ID_0 = 21,
667 AXI_WRITE_REQUESTS_ID_1 = 22,
668 AXI_WRITE_REQUESTS_ID_2 = 23,
669 AXI_WRITE_REQUESTS_ID_3 = 24,
670 AXI_WRITE_REQUESTS_ID_4 = 25,
671 AXI_WRITE_REQUESTS_ID_5 = 26,
672 AXI_WRITE_REQUESTS_ID_6 = 27,
673 AXI_WRITE_REQUESTS_ID_7 = 28,
674 AXI_WRITE_REQUESTS_ID_8 = 29,
675 AXI_WRITE_REQUESTS_ID_9 = 30,
676 AXI_WRITE_REQUESTS_ID_10 = 31,
677 AXI_WRITE_REQUESTS_ID_11 = 32,
678 AXI_WRITE_REQUESTS_ID_12 = 33,
679 AXI_WRITE_REQUESTS_ID_13 = 34,
680 AXI_WRITE_REQUESTS_ID_14 = 35,
681 AXI_WRITE_REQUESTS_ID_15 = 36,
682 AXI0_WRITE_REQUESTS_TOTAL = 37,
683 AXI1_WRITE_REQUESTS_TOTAL = 38,
684 AXI2_WRITE_REQUESTS_TOTAL = 39,
685 AXI3_WRITE_REQUESTS_TOTAL = 40,
686 AXI_WRITE_REQUESTS_TOTAL = 41,
687 AXI_TOTAL_REQUESTS = 42,
688 AXI_READ_DATA_BEATS_ID_0 = 43,
689 AXI_READ_DATA_BEATS_ID_1 = 44,
690 AXI_READ_DATA_BEATS_ID_2 = 45,
691 AXI_READ_DATA_BEATS_ID_3 = 46,
692 AXI_READ_DATA_BEATS_ID_4 = 47,
693 AXI_READ_DATA_BEATS_ID_5 = 48,
694 AXI_READ_DATA_BEATS_ID_6 = 49,
695 AXI_READ_DATA_BEATS_ID_7 = 50,
696 AXI_READ_DATA_BEATS_ID_8 = 51,
697 AXI_READ_DATA_BEATS_ID_9 = 52,
698 AXI_READ_DATA_BEATS_ID_10 = 53,
699 AXI_READ_DATA_BEATS_ID_11 = 54,
700 AXI_READ_DATA_BEATS_ID_12 = 55,
701 AXI_READ_DATA_BEATS_ID_13 = 56,
702 AXI_READ_DATA_BEATS_ID_14 = 57,
703 AXI_READ_DATA_BEATS_ID_15 = 58,
704 AXI0_READ_DATA_BEATS_TOTAL = 59,
705 AXI1_READ_DATA_BEATS_TOTAL = 60,
706 AXI2_READ_DATA_BEATS_TOTAL = 61,
707 AXI3_READ_DATA_BEATS_TOTAL = 62,
708 AXI_READ_DATA_BEATS_TOTAL = 63,
709 AXI_WRITE_DATA_BEATS_ID_0 = 64,
710 AXI_WRITE_DATA_BEATS_ID_1 = 65,
711 AXI_WRITE_DATA_BEATS_ID_2 = 66,
712 AXI_WRITE_DATA_BEATS_ID_3 = 67,
713 AXI_WRITE_DATA_BEATS_ID_4 = 68,
714 AXI_WRITE_DATA_BEATS_ID_5 = 69,
715 AXI_WRITE_DATA_BEATS_ID_6 = 70,
716 AXI_WRITE_DATA_BEATS_ID_7 = 71,
717 AXI_WRITE_DATA_BEATS_ID_8 = 72,
718 AXI_WRITE_DATA_BEATS_ID_9 = 73,
719 AXI_WRITE_DATA_BEATS_ID_10 = 74,
720 AXI_WRITE_DATA_BEATS_ID_11 = 75,
721 AXI_WRITE_DATA_BEATS_ID_12 = 76,
722 AXI_WRITE_DATA_BEATS_ID_13 = 77,
723 AXI_WRITE_DATA_BEATS_ID_14 = 78,
724 AXI_WRITE_DATA_BEATS_ID_15 = 79,
725 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
726 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
727 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
728 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
729 AXI_WRITE_DATA_BEATS_TOTAL = 84,
730 AXI_DATA_BEATS_TOTAL = 85,
731 CYCLES_HELD_OFF_ID_0 = 86,
732 CYCLES_HELD_OFF_ID_1 = 87,
733 CYCLES_HELD_OFF_ID_2 = 88,
734 CYCLES_HELD_OFF_ID_3 = 89,
735 CYCLES_HELD_OFF_ID_4 = 90,
736 CYCLES_HELD_OFF_ID_5 = 91,
737 CYCLES_HELD_OFF_ID_6 = 92,
738 CYCLES_HELD_OFF_ID_7 = 93,
739 CYCLES_HELD_OFF_ID_8 = 94,
740 CYCLES_HELD_OFF_ID_9 = 95,
741 CYCLES_HELD_OFF_ID_10 = 96,
742 CYCLES_HELD_OFF_ID_11 = 97,
743 CYCLES_HELD_OFF_ID_12 = 98,
744 CYCLES_HELD_OFF_ID_13 = 99,
745 CYCLES_HELD_OFF_ID_14 = 100,
746 CYCLES_HELD_OFF_ID_15 = 101,
747 AXI_READ_REQUEST_HELD_OFF = 102,
748 AXI_WRITE_REQUEST_HELD_OFF = 103,
749 AXI_REQUEST_HELD_OFF = 104,
750 AXI_WRITE_DATA_HELD_OFF = 105,
751 OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
752 OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
753 OCMEM_AXI_REQUEST_HELD_OFF = 108,
754 OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
755 ELAPSED_CYCLES_DDR = 110,
756 ELAPSED_CYCLES_OCMEM = 111,
757 };
758
759 enum a4xx_vfd_perfcounter_select {
760 VFD_UCHE_BYTE_FETCHED = 0,
761 VFD_UCHE_TRANS = 1,
762 VFD_FETCH_INSTRUCTIONS = 3,
763 VFD_BUSY_CYCLES = 5,
764 VFD_STALL_CYCLES_UCHE = 6,
765 VFD_STALL_CYCLES_HLSQ = 7,
766 VFD_STALL_CYCLES_VPC_BYPASS = 8,
767 VFD_STALL_CYCLES_VPC_ALLOC = 9,
768 VFD_MODE_0_FIBERS = 13,
769 VFD_MODE_1_FIBERS = 14,
770 VFD_MODE_2_FIBERS = 15,
771 VFD_MODE_3_FIBERS = 16,
772 VFD_MODE_4_FIBERS = 17,
773 VFD_BFIFO_STALL = 18,
774 VFD_NUM_VERTICES_TOTAL = 19,
775 VFD_PACKER_FULL = 20,
776 VFD_UCHE_REQUEST_FIFO_FULL = 21,
777 VFD_STARVE_CYCLES_PC = 22,
778 VFD_STARVE_CYCLES_UCHE = 23,
779 };
780
781 enum a4xx_vpc_perfcounter_select {
782 VPC_SP_LM_COMPONENTS = 2,
783 VPC_SP0_LM_BYTES = 3,
784 VPC_SP1_LM_BYTES = 4,
785 VPC_SP2_LM_BYTES = 5,
786 VPC_SP3_LM_BYTES = 6,
787 VPC_WORKING_CYCLES = 7,
788 VPC_STALL_CYCLES_LM = 8,
789 VPC_STARVE_CYCLES_RAS = 9,
790 VPC_STREAMOUT_CYCLES = 10,
791 VPC_UCHE_TRANSACTIONS = 12,
792 VPC_STALL_CYCLES_UCHE = 13,
793 VPC_BUSY_CYCLES = 14,
794 VPC_STARVE_CYCLES_SP = 15,
795 };
796
797 enum a4xx_vsc_perfcounter_select {
798 VSC_BUSY_CYCLES = 0,
799 VSC_WORKING_CYCLES = 1,
800 VSC_STALL_CYCLES_UCHE = 2,
801 VSC_STARVE_CYCLES_RAS = 3,
802 VSC_EOT_NUM = 4,
803 };
804
805 enum a4xx_tex_filter {
806 A4XX_TEX_NEAREST = 0,
807 A4XX_TEX_LINEAR = 1,
808 A4XX_TEX_ANISO = 2,
809 };
810
811 enum a4xx_tex_clamp {
812 A4XX_TEX_REPEAT = 0,
813 A4XX_TEX_CLAMP_TO_EDGE = 1,
814 A4XX_TEX_MIRROR_REPEAT = 2,
815 A4XX_TEX_CLAMP_TO_BORDER = 3,
816 A4XX_TEX_MIRROR_CLAMP = 4,
817 };
818
819 enum a4xx_tex_aniso {
820 A4XX_TEX_ANISO_1 = 0,
821 A4XX_TEX_ANISO_2 = 1,
822 A4XX_TEX_ANISO_4 = 2,
823 A4XX_TEX_ANISO_8 = 3,
824 A4XX_TEX_ANISO_16 = 4,
825 };
826
827 enum a4xx_tex_swiz {
828 A4XX_TEX_X = 0,
829 A4XX_TEX_Y = 1,
830 A4XX_TEX_Z = 2,
831 A4XX_TEX_W = 3,
832 A4XX_TEX_ZERO = 4,
833 A4XX_TEX_ONE = 5,
834 };
835
836 enum a4xx_tex_type {
837 A4XX_TEX_1D = 0,
838 A4XX_TEX_2D = 1,
839 A4XX_TEX_CUBE = 2,
840 A4XX_TEX_3D = 3,
841 };
842
843 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
844 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
846 {
847 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
848 }
849 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
850 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
851 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
852 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
853 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
854 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
855 #define A4XX_INT0_VFD_ERROR 0x00000040
856 #define A4XX_INT0_CP_SW_INT 0x00000080
857 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
858 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
859 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
860 #define A4XX_INT0_CP_HW_FAULT 0x00000800
861 #define A4XX_INT0_CP_DMA 0x00001000
862 #define A4XX_INT0_CP_IB2_INT 0x00002000
863 #define A4XX_INT0_CP_IB1_INT 0x00004000
864 #define A4XX_INT0_CP_RB_INT 0x00008000
865 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
866 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
867 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
868 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
869 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
870 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
871 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
872 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
873 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
874
875 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
876
877 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
878
879 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
880
881 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
882
883 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
884
885 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
886
887 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
888
889 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
890
891 #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
892
893 #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
894
895 #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
896
897 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
898
899 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
900 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
901 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
903 {
904 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
905 }
906 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
907 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
909 {
910 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
911 }
912
913 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
914
915 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
916
917 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
918
919 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
920
921 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
922 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
923 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
925 {
926 assert(!(val & 0x1f));
927 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
928 }
929 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
930 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)931 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
932 {
933 assert(!(val & 0x1f));
934 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
935 }
936 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000
937
938 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
939 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
940 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
941
942 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
943 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
944 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
945 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)946 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
947 {
948 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
949 }
950
951 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
952 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
953 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
954 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
955 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
956 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
957 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
958 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
959 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
960 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)961 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
962 {
963 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
964 }
965 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
966 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
967
REG_A4XX_RB_MRT(uint32_t i0)968 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
969
REG_A4XX_RB_MRT_CONTROL(uint32_t i0)970 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
971 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
972 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
973 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
974 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
975 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
976 #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)977 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
978 {
979 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
980 }
981 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
982 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)983 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
984 {
985 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
986 }
987
REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0)988 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
989 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
990 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)991 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
992 {
993 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
994 }
995 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
996 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)997 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
998 {
999 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1000 }
1001 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
1002 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)1003 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1004 {
1005 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
1006 }
1007 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
1008 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)1009 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1010 {
1011 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1012 }
1013 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
1014 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
1015 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)1016 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1017 {
1018 assert(!(val & 0xf));
1019 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1020 }
1021
REG_A4XX_RB_MRT_BASE(uint32_t i0)1022 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
1023
REG_A4XX_RB_MRT_CONTROL3(uint32_t i0)1024 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
1025 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
1026 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)1027 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
1028 {
1029 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
1030 }
1031
REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0)1032 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
1033 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
1034 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)1035 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1036 {
1037 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1038 }
1039 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1040 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)1041 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1042 {
1043 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1044 }
1045 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
1046 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)1047 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1048 {
1049 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1050 }
1051 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
1052 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)1053 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1054 {
1055 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1056 }
1057 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1058 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)1059 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1060 {
1061 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1062 }
1063 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1064 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)1065 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1066 {
1067 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1068 }
1069
1070 #define REG_A4XX_RB_BLEND_RED 0x000020f0
1071 #define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff
1072 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
A4XX_RB_BLEND_RED_UINT(uint32_t val)1073 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1074 {
1075 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1076 }
1077 #define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
1078 #define A4XX_RB_BLEND_RED_SINT__SHIFT 8
A4XX_RB_BLEND_RED_SINT(uint32_t val)1079 static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1080 {
1081 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1082 }
1083 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1084 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
A4XX_RB_BLEND_RED_FLOAT(float val)1085 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1086 {
1087 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1088 }
1089
1090 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1091 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1092 #define A4XX_RB_BLEND_RED_F32__SHIFT 0
A4XX_RB_BLEND_RED_F32(float val)1093 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1094 {
1095 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
1096 }
1097
1098 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2
1099 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
1100 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
A4XX_RB_BLEND_GREEN_UINT(uint32_t val)1101 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1102 {
1103 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1104 }
1105 #define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
1106 #define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8
A4XX_RB_BLEND_GREEN_SINT(uint32_t val)1107 static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1108 {
1109 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1110 }
1111 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1112 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
A4XX_RB_BLEND_GREEN_FLOAT(float val)1113 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1114 {
1115 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1116 }
1117
1118 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1119 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1120 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
A4XX_RB_BLEND_GREEN_F32(float val)1121 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1122 {
1123 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
1124 }
1125
1126 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4
1127 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
1128 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
A4XX_RB_BLEND_BLUE_UINT(uint32_t val)1129 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1130 {
1131 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1132 }
1133 #define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
1134 #define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8
A4XX_RB_BLEND_BLUE_SINT(uint32_t val)1135 static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1136 {
1137 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1138 }
1139 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1140 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
A4XX_RB_BLEND_BLUE_FLOAT(float val)1141 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1142 {
1143 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1144 }
1145
1146 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1147 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1148 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
A4XX_RB_BLEND_BLUE_F32(float val)1149 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1150 {
1151 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
1152 }
1153
1154 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
1155 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
1156 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)1157 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1158 {
1159 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1160 }
1161 #define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
1162 #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8
A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)1163 static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1164 {
1165 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1166 }
1167 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1168 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
A4XX_RB_BLEND_ALPHA_FLOAT(float val)1169 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1170 {
1171 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1172 }
1173
1174 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1175 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1176 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
A4XX_RB_BLEND_ALPHA_F32(float val)1177 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1178 {
1179 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
1180 }
1181
1182 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
1183 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
1184 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)1185 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
1186 {
1187 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
1188 }
1189 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
1190 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
1191 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)1192 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1193 {
1194 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
1195 }
1196
1197 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
1198 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
1199 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)1200 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
1201 {
1202 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
1203 }
1204 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
1205 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
1206 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)1207 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
1208 {
1209 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
1210 }
1211
1212 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
1213 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1214 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
1215 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)1216 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
1217 {
1218 assert(!(val & 0x3));
1219 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
1220 }
1221
1222 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
1223 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
1224 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)1225 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
1226 {
1227 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
1228 }
1229 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
1230 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)1231 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
1232 {
1233 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
1234 }
1235 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
1236 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)1237 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
1238 {
1239 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
1240 }
1241 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
1242 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)1243 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
1244 {
1245 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
1246 }
1247 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
1248 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)1249 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
1250 {
1251 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
1252 }
1253 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
1254 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)1255 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
1256 {
1257 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
1258 }
1259 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
1260 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)1261 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
1262 {
1263 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
1264 }
1265 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
1266 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)1267 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
1268 {
1269 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
1270 }
1271
1272 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
1273 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
1274 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)1275 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1276 {
1277 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1278 }
1279 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
1280 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)1281 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1282 {
1283 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
1284 }
1285 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1286 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)1287 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1288 {
1289 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1290 }
1291 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1292 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)1293 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1294 {
1295 assert(!(val & 0x3fff));
1296 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1297 }
1298
1299 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
1300 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
1301 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)1302 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1303 {
1304 assert(!(val & 0x1f));
1305 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
1306 }
1307
1308 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
1309 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1310 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)1311 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1312 {
1313 assert(!(val & 0x1f));
1314 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1315 }
1316
1317 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
1318 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1319 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)1320 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
1321 {
1322 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1323 }
1324 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1325 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)1326 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1327 {
1328 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
1329 }
1330 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1331 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)1332 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1333 {
1334 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1335 }
1336 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1337 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)1338 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1339 {
1340 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1341 }
1342 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1343 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)1344 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1345 {
1346 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1347 }
1348 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
1349 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)1350 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
1351 {
1352 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
1353 }
1354
1355 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
1356 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1357 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)1358 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
1359 {
1360 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
1361 }
1362 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
1363
1364 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
1365 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1366 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1367 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1368 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1369 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)1370 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1371 {
1372 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1373 }
1374 #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1375 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
1376 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
1377 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1378
1379 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
1380
1381 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
1382 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1383 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)1384 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
1385 {
1386 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1387 }
1388 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
1389 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)1390 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1391 {
1392 assert(!(val & 0xfff));
1393 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1394 }
1395
1396 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
1397 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
1398 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
A4XX_RB_DEPTH_PITCH(uint32_t val)1399 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
1400 {
1401 assert(!(val & 0x1f));
1402 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
1403 }
1404
1405 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
1406 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
1407 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
A4XX_RB_DEPTH_PITCH2(uint32_t val)1408 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
1409 {
1410 assert(!(val & 0x1f));
1411 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
1412 }
1413
1414 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
1415 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1416 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1417 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1418 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1419 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)1420 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1421 {
1422 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
1423 }
1424 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1425 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)1426 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1427 {
1428 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
1429 }
1430 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1431 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)1432 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1433 {
1434 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1435 }
1436 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1437 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)1438 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1439 {
1440 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1441 }
1442 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1443 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)1444 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1445 {
1446 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1447 }
1448 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1449 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)1450 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1451 {
1452 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1453 }
1454 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1455 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)1456 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1457 {
1458 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1459 }
1460 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1461 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)1462 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1463 {
1464 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1465 }
1466
1467 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
1468 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
1469
1470 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
1471 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
1472 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
1473 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)1474 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1475 {
1476 assert(!(val & 0xfff));
1477 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1478 }
1479
1480 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
1481 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
1482 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
A4XX_RB_STENCIL_PITCH(uint32_t val)1483 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
1484 {
1485 assert(!(val & 0x1f));
1486 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
1487 }
1488
1489 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
1490 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1491 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)1492 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1493 {
1494 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
1495 }
1496 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1497 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)1498 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1499 {
1500 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1501 }
1502 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1503 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)1504 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1505 {
1506 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1507 }
1508
1509 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
1510 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1511 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)1512 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1513 {
1514 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1515 }
1516 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1517 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)1518 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1519 {
1520 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1521 }
1522 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1523 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)1524 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1525 {
1526 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1527 }
1528
1529 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
1530 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
1531 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
1532 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
A4XX_RB_BIN_OFFSET_X(uint32_t val)1533 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
1534 {
1535 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
1536 }
1537 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
1538 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
A4XX_RB_BIN_OFFSET_Y(uint32_t val)1539 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
1540 {
1541 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
1542 }
1543
REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0)1544 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1545
REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0)1546 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1547
REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0)1548 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
1549
1550 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
1551
1552 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
1553
REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0)1554 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1555
REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0)1556 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1557
REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0)1558 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1559
REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0)1560 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1561
REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0)1562 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1563
REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0)1564 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1565
REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0)1566 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1567
REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0)1568 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1569
1570 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
1571
1572 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
1573
1574 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
1575
1576 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
1577
1578 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
1579
1580 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
1581
1582 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
1583
1584 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
1585
1586 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
1587
1588 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
1589
1590 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
1591
1592 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1593
1594 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1595
1596 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1597
1598 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1599
1600 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1601
1602 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1603
1604 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
1605
1606 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1607
1608 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1609
1610 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1611
1612 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1613
1614 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1615
1616 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1617
1618 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1619
1620 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1621
1622 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1623
1624 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1625
1626 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1627
1628 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1629
1630 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1631
1632 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1633
1634 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1635
1636 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1637
1638 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1639
1640 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1641
1642 #define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
1643 #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
1644 #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
1645
1646 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1647
1648 #define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
1649
1650 #define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
1651
1652 #define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
1653
1654 #define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
1655
1656 #define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
1657
1658 #define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
1659
1660 #define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
1661
1662 #define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
1663
1664 #define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
1665
1666 #define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
1667
1668 #define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
1669
1670 #define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
1671
1672 #define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
1673
1674 #define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
1675
1676 #define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
1677
1678 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
1679
1680 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
1681
1682 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
1683
1684 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
1685
1686 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
1687
1688 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
1689
1690 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
1691
1692 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
1693
1694 #define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
1695
1696 #define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
1697
1698 #define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
1699
1700 #define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
1701
1702 #define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
1703
1704 #define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
1705
1706 #define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
1707
1708 #define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
1709
1710 #define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
1711
1712 #define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
1713
1714 #define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
1715
1716 #define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
1717
1718 #define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
1719
1720 #define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
1721
1722 #define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
1723
1724 #define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
1725
1726 #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
1727
1728 #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
1729
1730 #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
1731
1732 #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
1733
1734 #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
1735
1736 #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
1737
1738 #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
1739
1740 #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
1741
1742 #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
1743
1744 #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
1745
1746 #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
1747
1748 #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
1749
1750 #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
1751
1752 #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
1753
1754 #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
1755
1756 #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
1757
1758 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
1759
1760 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
1761
1762 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
1763
1764 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
1765
1766 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
1767
1768 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
1769
1770 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
1771
1772 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
1773
1774 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
1775
1776 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
1777
1778 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
1779
1780 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
1781
1782 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
1783
1784 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
1785
1786 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
1787
1788 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
1789
1790 #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
1791
1792 #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
1793
1794 #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
1795
1796 #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
1797
1798 #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
1799
1800 #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
1801
1802 #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
1803
1804 #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
1805
1806 #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
1807
1808 #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
1809
1810 #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
1811
1812 #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
1813
1814 #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
1815
1816 #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
1817
1818 #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
1819
1820 #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
1821
1822 #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
1823
1824 #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
1825
1826 #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
1827
1828 #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
1829
1830 #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
1831
1832 #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
1833
1834 #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
1835
1836 #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
1837
1838 #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
1839
1840 #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
1841
1842 #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
1843
1844 #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
1845
1846 #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
1847
1848 #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
1849
1850 #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
1851
1852 #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
1853
1854 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
1855
1856 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
1857
1858 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
1859
1860 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
1861
1862 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
1863
1864 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
1865
1866 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
1867
1868 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
1869
1870 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
1871
1872 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
1873
1874 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
1875
1876 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
1877
1878 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
1879
1880 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
1881
1882 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
1883
1884 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
1885
1886 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1887
1888 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1889
1890 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1891
1892 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1893
1894 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
1895
1896 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
1897
1898 #define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
1899
1900 #define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
1901
1902 #define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
1903
1904 #define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
1905
1906 #define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
1907
1908 #define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
1909
1910 #define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
1911
1912 #define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
1913
1914 #define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
1915
1916 #define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
1917
1918 #define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
1919
1920 #define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
1921
1922 #define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
1923
1924 #define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
1925
1926 #define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
1927
1928 #define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
1929
1930 #define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
1931
1932 #define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
1933
1934 #define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
1935
1936 #define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
1937
1938 #define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
1939
1940 #define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
1941
1942 #define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
1943
1944 #define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
1945
1946 #define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
1947
1948 #define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
1949
1950 #define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
1951
1952 #define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
1953
1954 #define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
1955
1956 #define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
1957
1958 #define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
1959
1960 #define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
1961
1962 #define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
1963
1964 #define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
1965
1966 #define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
1967
1968 #define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
1969
1970 #define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
1971
1972 #define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
1973
1974 #define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
1975
1976 #define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
1977
1978 #define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
1979
1980 #define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
1981
1982 #define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
1983
1984 #define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
1985
1986 #define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
1987
1988 #define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
1989
1990 #define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
1991
1992 #define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
1993
1994 #define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
1995
1996 #define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
1997
1998 #define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
1999
2000 #define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
2001
2002 #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
2003
2004 #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
2005
2006 #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
2007
2008 #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
2009
2010 #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
2011
2012 #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
2013
2014 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
2015
2016 #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
2017
2018 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
2019
2020 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
2021
REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0)2022 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2023
REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0)2024 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2025
REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0)2026 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2027
REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0)2028 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2029
REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0)2030 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2031
REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0)2032 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2033
REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0)2034 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2035
REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0)2036 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2037
REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0)2038 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2039
REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0)2040 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2041
REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0)2042 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2043
REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0)2044 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2045
REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0)2046 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2047
REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0)2048 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2049
REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0)2050 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2051
REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0)2052 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2053
2054 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
2055
2056 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
2057
2058 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
2059
2060 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
2061
2062 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
2063
2064 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
2065
REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0)2066 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2067
REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)2068 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2069
2070 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
2071
2072 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
2073
2074 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
2075
2076 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
2077
2078 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
2079
2080 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
2081
2082 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
2083
2084 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
2085
2086 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
2087
2088 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
2089
2090 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
2091
2092 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
2093
2094 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
2095
2096 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
2097
2098 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
2099
2100 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
2101
2102 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
2103
2104 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
2105
2106 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
2107
2108 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
2109
2110 #define REG_A4XX_RBBM_STATUS 0x00000191
2111 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
2112 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
2113 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
2114 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
2115 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
2116 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
2117 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
2118 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
2119 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
2120 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
2121 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
2122 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
2123 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
2124 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
2125 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
2126 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
2127 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
2128 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
2129 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
2130 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
2131 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
2132
2133 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
2134
2135 #define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
2136 #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
2137
2138 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
2139
2140 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
2141
2142 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
2143
2144 #define REG_A4XX_CP_RB_BASE 0x00000200
2145
2146 #define REG_A4XX_CP_RB_CNTL 0x00000201
2147
2148 #define REG_A4XX_CP_RB_WPTR 0x00000205
2149
2150 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
2151
2152 #define REG_A4XX_CP_RB_RPTR 0x00000204
2153
2154 #define REG_A4XX_CP_IB1_BASE 0x00000206
2155
2156 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
2157
2158 #define REG_A4XX_CP_IB2_BASE 0x00000208
2159
2160 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
2161
2162 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
2163
2164 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
2165
2166 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
2167
2168 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
2169
2170 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
2171
2172 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
2173
2174 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
2175
2176 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
2177
2178 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
2179
2180 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
2181
2182 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
2183
2184 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
2185
2186 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
2187
2188 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
2189
2190 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
2191
2192 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
2193
2194 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
2195
2196 #define REG_A4XX_CP_PREEMPT 0x0000022a
2197
2198 #define REG_A4XX_CP_CNTL 0x0000022c
2199
2200 #define REG_A4XX_CP_ME_CNTL 0x0000022d
2201
2202 #define REG_A4XX_CP_DEBUG 0x0000022e
2203
2204 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
2205
2206 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
2207
REG_A4XX_CP_PROTECT(uint32_t i0)2208 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2209
REG_A4XX_CP_PROTECT_REG(uint32_t i0)2210 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2211 #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
2212 #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)2213 static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
2214 {
2215 return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;
2216 }
2217 #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
2218 #define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)2219 static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
2220 {
2221 return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
2222 }
2223 #define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
2224 #define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000
2225
2226 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
2227
2228 #define REG_A4XX_CP_ST_BASE 0x000004c0
2229
2230 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
2231
2232 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
2233
2234 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
2235
2236 #define REG_A4XX_CP_HW_FAULT 0x000004d8
2237
2238 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
2239
2240 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
2241
2242 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
2243
2244 #define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
2245
2246 #define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
2247
2248 #define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
2249
2250 #define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
2251
2252 #define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
2253
2254 #define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
2255
2256 #define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
2257
2258 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
2259
REG_A4XX_CP_SCRATCH(uint32_t i0)2260 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2261
REG_A4XX_CP_SCRATCH_REG(uint32_t i0)2262 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2263
2264 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
2265
2266 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
2267
2268 #define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
2269
2270 #define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
2271
2272 #define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
2273
2274 #define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
2275
2276 #define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
2277
2278 #define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
2279
2280 #define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
2281
2282 #define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
2283
2284 #define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
2285
2286 #define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
2287
2288 #define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
2289
2290 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
2291
2292 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
2293 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
2294
2295 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
2296 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
2297 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
2298 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
2299
2300 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
2301 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
2302 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)2303 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2304 {
2305 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2306 }
2307 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
2308 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
2309 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2310 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)2311 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2312 {
2313 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2314 }
2315 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2316 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)2317 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2318 {
2319 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2320 }
2321 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2322 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)2323 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2324 {
2325 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2326 }
2327 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2328 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)2329 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2330 {
2331 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2332 }
2333 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2334 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
2335
2336 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
2337 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2338 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)2339 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2340 {
2341 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2342 }
2343 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
2344 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)2345 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2346 {
2347 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2348 }
2349
2350 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
2351 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
2352 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)2353 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2354 {
2355 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
2356 }
2357 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2358 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)2359 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2360 {
2361 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2362 }
2363 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
2364 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)2365 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2366 {
2367 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2368 }
2369
REG_A4XX_SP_VS_OUT(uint32_t i0)2370 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2371
REG_A4XX_SP_VS_OUT_REG(uint32_t i0)2372 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2373 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
2374 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)2375 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2376 {
2377 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
2378 }
2379 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2380 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)2381 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2382 {
2383 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2384 }
2385 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
2386 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)2387 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2388 {
2389 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
2390 }
2391 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2392 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)2393 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2394 {
2395 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2396 }
2397
REG_A4XX_SP_VS_VPC_DST(uint32_t i0)2398 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2399
REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0)2400 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2401 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2402 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)2403 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2404 {
2405 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2406 }
2407 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2408 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)2409 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2410 {
2411 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2412 }
2413 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2414 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)2415 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2416 {
2417 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2418 }
2419 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2420 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)2421 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2422 {
2423 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2424 }
2425
2426 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
2427 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2428 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)2429 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2430 {
2431 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2432 }
2433 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2434 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)2435 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2436 {
2437 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2438 }
2439
2440 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
2441
2442 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
2443
2444 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
2445
2446 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
2447
2448 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
2449 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
2450 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)2451 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2452 {
2453 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2454 }
2455 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
2456 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2457 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2458 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)2459 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2460 {
2461 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2462 }
2463 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2464 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)2465 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2466 {
2467 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2468 }
2469 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2470 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)2471 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2472 {
2473 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2474 }
2475 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2476 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)2477 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2478 {
2479 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2480 }
2481 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2482 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
2483
2484 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
2485 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2486 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)2487 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2488 {
2489 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2490 }
2491 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
2492 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
2493 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
2494
2495 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
2496 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2497 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)2498 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2499 {
2500 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2501 }
2502 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2503 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)2504 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2505 {
2506 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2507 }
2508
2509 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
2510
2511 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
2512
2513 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
2514
2515 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
2516
2517 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
2518 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
2519 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)2520 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2521 {
2522 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
2523 }
2524 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
2525 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
2526 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)2527 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2528 {
2529 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2530 }
2531 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
2532 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)2533 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
2534 {
2535 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
2536 }
2537
REG_A4XX_SP_FS_MRT(uint32_t i0)2538 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2539
REG_A4XX_SP_FS_MRT_REG(uint32_t i0)2540 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2541 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
2542 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
A4XX_SP_FS_MRT_REG_REGID(uint32_t val)2543 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
2544 {
2545 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
2546 }
2547 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2548 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
2549 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)2550 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
2551 {
2552 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
2553 }
2554 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
2555
2556 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
2557
2558 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
2559
2560 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
2561
2562 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
2563
2564 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
2565
2566 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
2567
2568 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
2569
2570 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
2571 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2572 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)2573 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2574 {
2575 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2576 }
2577 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2578 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)2579 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2580 {
2581 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2582 }
2583
2584 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
2585
2586 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
2587
2588 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
2589
2590 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
2591
2592 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
2593 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
2594 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)2595 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
2596 {
2597 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
2598 }
2599 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2600 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)2601 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2602 {
2603 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
2604 }
2605
REG_A4XX_SP_DS_OUT(uint32_t i0)2606 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2607
REG_A4XX_SP_DS_OUT_REG(uint32_t i0)2608 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2609 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
2610 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)2611 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
2612 {
2613 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
2614 }
2615 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2616 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)2617 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
2618 {
2619 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
2620 }
2621 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
2622 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)2623 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
2624 {
2625 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
2626 }
2627 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2628 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)2629 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
2630 {
2631 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
2632 }
2633
REG_A4XX_SP_DS_VPC_DST(uint32_t i0)2634 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2635
REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0)2636 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2637 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2638 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)2639 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
2640 {
2641 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
2642 }
2643 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2644 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)2645 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
2646 {
2647 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
2648 }
2649 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2650 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)2651 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
2652 {
2653 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
2654 }
2655 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2656 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)2657 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
2658 {
2659 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
2660 }
2661
2662 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
2663 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2664 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)2665 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2666 {
2667 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2668 }
2669 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2670 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)2671 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2672 {
2673 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2674 }
2675
2676 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
2677
2678 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
2679
2680 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
2681
2682 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
2683
2684 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
2685 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
2686 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)2687 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
2688 {
2689 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
2690 }
2691 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
2692 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)2693 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
2694 {
2695 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
2696 }
2697 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2698 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)2699 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2700 {
2701 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
2702 }
2703
REG_A4XX_SP_GS_OUT(uint32_t i0)2704 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2705
REG_A4XX_SP_GS_OUT_REG(uint32_t i0)2706 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2707 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
2708 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)2709 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
2710 {
2711 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
2712 }
2713 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2714 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)2715 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
2716 {
2717 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
2718 }
2719 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
2720 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)2721 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
2722 {
2723 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
2724 }
2725 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2726 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)2727 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
2728 {
2729 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
2730 }
2731
REG_A4XX_SP_GS_VPC_DST(uint32_t i0)2732 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2733
REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0)2734 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2735 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2736 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)2737 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
2738 {
2739 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
2740 }
2741 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2742 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)2743 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
2744 {
2745 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
2746 }
2747 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2748 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)2749 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
2750 {
2751 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
2752 }
2753 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2754 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)2755 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
2756 {
2757 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
2758 }
2759
2760 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
2761 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2762 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)2763 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2764 {
2765 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2766 }
2767 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2768 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)2769 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2770 {
2771 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2772 }
2773
2774 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
2775
2776 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
2777
2778 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
2779
2780 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
2781
2782 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
2783
2784 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
2785
2786 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
2787
2788 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
2789
2790 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
2791
2792 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
2793
2794 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
2795
2796 #define REG_A4XX_VPC_ATTR 0x00002140
2797 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
2798 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
A4XX_VPC_ATTR_TOTALATTR(uint32_t val)2799 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
2800 {
2801 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
2802 }
2803 #define A4XX_VPC_ATTR_PSIZE 0x00000200
2804 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
2805 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)2806 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2807 {
2808 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
2809 }
2810 #define A4XX_VPC_ATTR_ENABLE 0x02000000
2811
2812 #define REG_A4XX_VPC_PACK 0x00002141
2813 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
2814 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)2815 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
2816 {
2817 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
2818 }
2819 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
2820 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)2821 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2822 {
2823 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2824 }
2825 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
2826 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)2827 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2828 {
2829 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2830 }
2831
REG_A4XX_VPC_VARYING_INTERP(uint32_t i0)2832 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2833
REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0)2834 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2835
REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0)2836 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2837
REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0)2838 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2839
2840 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
2841
2842 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
2843 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
2844 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)2845 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2846 {
2847 assert(!(val & 0x1f));
2848 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
2849 }
2850 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
2851 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)2852 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2853 {
2854 assert(!(val & 0x1f));
2855 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
2856 }
2857
2858 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
2859
2860 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
2861
2862 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
2863
REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0)2864 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2865
REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0)2866 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2867 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2868 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)2869 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2870 {
2871 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
2872 }
2873 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2874 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)2875 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2876 {
2877 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2878 }
2879 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
2880 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)2881 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2882 {
2883 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
2884 }
2885 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
2886 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)2887 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2888 {
2889 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
2890 }
2891
REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0)2892 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2893
REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0)2894 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2895
REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0)2896 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2897
REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0)2898 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2899
2900 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
2901
2902 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
2903
2904 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
2905
2906 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
2907
2908 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
2909
2910 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
2911
2912 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
2913
2914 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
2915
2916 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
2917
2918 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
2919
2920 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
2921
2922 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
2923
2924 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
2925
2926 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
2927
2928 #define REG_A4XX_VFD_CONTROL_0 0x00002200
2929 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
2930 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)2931 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
2932 {
2933 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
2934 }
2935 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
2936 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)2937 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
2938 {
2939 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
2940 }
2941 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
2942 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)2943 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
2944 {
2945 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
2946 }
2947 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
2948 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)2949 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
2950 {
2951 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
2952 }
2953
2954 #define REG_A4XX_VFD_CONTROL_1 0x00002201
2955 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
2956 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)2957 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
2958 {
2959 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
2960 }
2961 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
2962 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)2963 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
2964 {
2965 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
2966 }
2967 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
2968 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)2969 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
2970 {
2971 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
2972 }
2973
2974 #define REG_A4XX_VFD_CONTROL_2 0x00002202
2975
2976 #define REG_A4XX_VFD_CONTROL_3 0x00002203
2977 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
2978 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)2979 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
2980 {
2981 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
2982 }
2983 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
2984 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)2985 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
2986 {
2987 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
2988 }
2989 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
2990 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)2991 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
2992 {
2993 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
2994 }
2995
2996 #define REG_A4XX_VFD_CONTROL_4 0x00002204
2997
2998 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
2999
REG_A4XX_VFD_FETCH(uint32_t i0)3000 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
3001
REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0)3002 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
3003 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
3004 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)3005 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
3006 {
3007 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
3008 }
3009 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
3010 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)3011 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
3012 {
3013 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
3014 }
3015 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
3016 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
3017
REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0)3018 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
3019
REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0)3020 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
3021 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
3022 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)3023 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
3024 {
3025 return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
3026 }
3027
REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0)3028 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
3029 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
3030 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)3031 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
3032 {
3033 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
3034 }
3035
REG_A4XX_VFD_DECODE(uint32_t i0)3036 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3037
REG_A4XX_VFD_DECODE_INSTR(uint32_t i0)3038 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3039 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
3040 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)3041 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
3042 {
3043 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
3044 }
3045 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
3046 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
3047 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)3048 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
3049 {
3050 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
3051 }
3052 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
3053 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)3054 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
3055 {
3056 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
3057 }
3058 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
3059 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
3060 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)3061 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3062 {
3063 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
3064 }
3065 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
3066 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)3067 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
3068 {
3069 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
3070 }
3071 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
3072 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
3073
3074 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
3075
3076 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
3077
3078 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
3079
3080 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
3081
3082 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
3083
3084 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
3085
3086 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
3087
3088 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
3089
3090 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
3091
3092 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
3093
3094 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
3095
3096 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
3097 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
3098 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)3099 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
3100 {
3101 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
3102 }
3103 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
3104 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)3105 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
3106 {
3107 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
3108 }
3109 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
3110 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)3111 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
3112 {
3113 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
3114 }
3115 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
3116 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)3117 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
3118 {
3119 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
3120 }
3121
3122 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
3123
3124 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
3125
3126 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
3127
3128 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
3129
3130 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
3131
3132 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
3133
3134 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
3135
3136 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
3137
3138 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
3139
3140 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
3141
3142 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
3143
3144 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
3145
3146 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
3147
3148 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
3149
3150 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
3151
3152 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
3153
3154 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
3155
3156 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
3157
3158 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
3159
3160 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
3161 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
3162 #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000
3163 #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
3164 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
3165
3166 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
3167 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
3168
3169 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
3170 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
3171 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)3172 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
3173 {
3174 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
3175 }
3176 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
3177 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)3178 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
3179 {
3180 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
3181 }
3182
3183 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
3184 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
3185 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)3186 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
3187 {
3188 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
3189 }
3190
3191 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
3192 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
3193 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
A4XX_GRAS_CL_VPORT_XSCALE_0(float val)3194 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
3195 {
3196 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
3197 }
3198
3199 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
3200 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
3201 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)3202 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
3203 {
3204 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
3205 }
3206
3207 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
3208 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
3209 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
A4XX_GRAS_CL_VPORT_YSCALE_0(float val)3210 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
3211 {
3212 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
3213 }
3214
3215 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
3216 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
3217 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)3218 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
3219 {
3220 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
3221 }
3222
3223 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
3224 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
3225 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)3226 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
3227 {
3228 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
3229 }
3230
3231 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
3232 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
3233 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)3234 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
3235 {
3236 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
3237 }
3238 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
3239 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)3240 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
3241 {
3242 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
3243 }
3244
3245 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
3246 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
3247 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
A4XX_GRAS_SU_POINT_SIZE(float val)3248 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
3249 {
3250 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
3251 }
3252
3253 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
3254 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
3255 #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
3256
3257 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
3258 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
3259 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)3260 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
3261 {
3262 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
3263 }
3264
3265 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
3266 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
3267 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)3268 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
3269 {
3270 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
3271 }
3272
3273 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
3274 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
3275 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)3276 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
3277 {
3278 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
3279 }
3280
3281 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
3282 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
3283 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)3284 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
3285 {
3286 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
3287 }
3288
3289 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
3290 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
3291 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
3292 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
3293 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
3294 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)3295 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
3296 {
3297 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
3298 }
3299 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
3300 #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000
3301 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
3302
3303 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
3304 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
3305 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)3306 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
3307 {
3308 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
3309 }
3310 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
3311 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)3312 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
3313 {
3314 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
3315 }
3316 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
3317 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
3318 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)3319 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
3320 {
3321 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
3322 }
3323
3324 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
3325 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3326 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
3327 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)3328 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
3329 {
3330 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
3331 }
3332 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
3333 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)3334 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
3335 {
3336 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
3337 }
3338
3339 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
3340 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3341 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
3342 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)3343 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
3344 {
3345 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
3346 }
3347 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
3348 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)3349 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
3350 {
3351 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
3352 }
3353
3354 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
3355 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3356 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
3357 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)3358 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3359 {
3360 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3361 }
3362 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
3363 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)3364 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3365 {
3366 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3367 }
3368
3369 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
3370 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3371 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
3372 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)3373 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3374 {
3375 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3376 }
3377 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
3378 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)3379 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3380 {
3381 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3382 }
3383
3384 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
3385 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
3386 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
3387 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)3388 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
3389 {
3390 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
3391 }
3392 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
3393 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)3394 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
3395 {
3396 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
3397 }
3398
3399 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
3400 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
3401 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
3402 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)3403 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
3404 {
3405 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
3406 }
3407 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
3408 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)3409 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
3410 {
3411 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
3412 }
3413
3414 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
3415
3416 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
3417
3418 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
3419
3420 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
3421
3422 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
3423
3424 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
3425
3426 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
3427
3428 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
3429
3430 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
3431
3432 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
3433
3434 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
3435
3436 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
3437
3438 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
3439
3440 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
3441
3442 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
3443
3444 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
3445
3446 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
3447
3448 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
3449
3450 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
3451
3452 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
3453
3454 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
3455
3456 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
3457
3458 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
3459
3460 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
3461
3462 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
3463
3464 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
3465
3466 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
3467
3468 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
3469 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
3470 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)3471 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
3472 {
3473 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
3474 }
3475 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
3476 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
3477 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
3478 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
3479 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
3480 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)3481 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
3482 {
3483 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
3484 }
3485 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
3486 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
3487 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
3488 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
3489
3490 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
3491 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
3492 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)3493 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
3494 {
3495 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
3496 }
3497 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
3498 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
3499 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
3500 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)3501 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
3502 {
3503 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
3504 }
3505 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
3506 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)3507 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
3508 {
3509 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
3510 }
3511
3512 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
3513 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
3514 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)3515 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3516 {
3517 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
3518 }
3519 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
3520 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)3521 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3522 {
3523 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3524 }
3525 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
3526 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)3527 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
3528 {
3529 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
3530 }
3531 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
3532 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)3533 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
3534 {
3535 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
3536 }
3537
3538 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
3539 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
3540 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)3541 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
3542 {
3543 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
3544 }
3545
3546 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
3547
3548 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
3549 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3550 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)3551 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3552 {
3553 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
3554 }
3555 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3556 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)3557 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3558 {
3559 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3560 }
3561 #define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000
3562 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
3563 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3564 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)3565 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3566 {
3567 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3568 }
3569 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3570 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)3571 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3572 {
3573 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
3574 }
3575
3576 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
3577 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3578 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)3579 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3580 {
3581 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
3582 }
3583 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3584 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)3585 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3586 {
3587 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3588 }
3589 #define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000
3590 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
3591 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3592 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)3593 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3594 {
3595 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3596 }
3597 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3598 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)3599 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3600 {
3601 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
3602 }
3603
3604 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
3605 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3606 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)3607 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3608 {
3609 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
3610 }
3611 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3612 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)3613 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3614 {
3615 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3616 }
3617 #define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000
3618 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
3619 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3620 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)3621 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3622 {
3623 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3624 }
3625 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3626 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)3627 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3628 {
3629 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
3630 }
3631
3632 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
3633 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3634 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)3635 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3636 {
3637 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
3638 }
3639 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3640 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)3641 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3642 {
3643 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3644 }
3645 #define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000
3646 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
3647 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3648 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)3649 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3650 {
3651 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3652 }
3653 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3654 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)3655 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3656 {
3657 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
3658 }
3659
3660 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
3661 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3662 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)3663 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3664 {
3665 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
3666 }
3667 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3668 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)3669 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3670 {
3671 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3672 }
3673 #define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000
3674 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
3675 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3676 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)3677 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3678 {
3679 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3680 }
3681 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3682 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)3683 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3684 {
3685 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
3686 }
3687
3688 #define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca
3689 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3690 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0
A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)3691 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3692 {
3693 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK;
3694 }
3695 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3696 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)3697 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3698 {
3699 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3700 }
3701 #define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000
3702 #define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000
3703 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3704 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)3705 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3706 {
3707 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3708 }
3709 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3710 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24
A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)3711 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3712 {
3713 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK;
3714 }
3715
3716 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
3717 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003
3718 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0
A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)3719 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)
3720 {
3721 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK;
3722 }
3723 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
3724 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2
A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)3725 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)
3726 {
3727 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK;
3728 }
3729 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
3730 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12
A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)3731 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)
3732 {
3733 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK;
3734 }
3735 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
3736 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22
A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)3737 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)
3738 {
3739 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK;
3740 }
3741
3742 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
3743 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff
3744 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0
A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)3745 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)
3746 {
3747 return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK;
3748 }
3749
3750 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
3751
3752 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
3753 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff
3754 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0
A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)3755 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)
3756 {
3757 return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK;
3758 }
3759
3760 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
3761
3762 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
3763 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff
3764 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0
A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)3765 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
3766 {
3767 return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK;
3768 }
3769
3770 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
3771
3772 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
3773 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff
3774 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)3775 static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
3776 {
3777 return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
3778 }
3779 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
3780 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)3781 static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
3782 {
3783 return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK;
3784 }
3785
3786 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
3787
3788 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
3789
3790 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
3791
3792 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
3793
3794 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
3795
3796 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
3797
3798 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
3799
3800 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
3801 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
3802
3803 #define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08
3804
3805 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
3806
3807 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
3808
3809 #define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
3810
3811 #define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
3812
3813 #define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
3814
3815 #define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
3816
3817 #define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
3818
3819 #define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
3820
3821 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
3822
3823 #define REG_A4XX_PC_BIN_BASE 0x000021c0
3824
3825 #define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2
3826 #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
3827 #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)3828 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
3829 {
3830 return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;
3831 }
3832 #define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
3833 #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22
A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)3834 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
3835 {
3836 return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;
3837 }
3838
3839 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
3840 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
3841 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)3842 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
3843 {
3844 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
3845 }
3846 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
3847 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
3848 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
3849
3850 #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
3851 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3852 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)3853 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3854 {
3855 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
3856 }
3857 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
3858 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)3859 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3860 {
3861 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
3862 }
3863 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
3864
3865 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
3866
3867 #define REG_A4XX_PC_GS_PARAM 0x000021e5
3868 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3869 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)3870 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3871 {
3872 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3873 }
3874 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3875 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)3876 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3877 {
3878 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
3879 }
3880 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
3881 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)3882 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3883 {
3884 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
3885 }
3886 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
3887
3888 #define REG_A4XX_PC_HS_PARAM 0x000021e7
3889 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
3890 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)3891 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3892 {
3893 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3894 }
3895 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
3896 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)3897 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3898 {
3899 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
3900 }
3901 #define A4XX_PC_HS_PARAM_CW 0x00800000
3902 #define A4XX_PC_HS_PARAM_CONNECTED 0x01000000
3903
3904 #define REG_A4XX_VBIF_VERSION 0x00003000
3905
3906 #define REG_A4XX_VBIF_CLKON 0x00003001
3907 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
3908
3909 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
3910
3911 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
3912
3913 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
3914
3915 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
3916
3917 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
3918
3919 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
3920
3921 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
3922
3923 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
3924
3925 #define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
3926
3927 #define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
3928
3929 #define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
3930
3931 #define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
3932
3933 #define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
3934
3935 #define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
3936
3937 #define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
3938
3939 #define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
3940
3941 #define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
3942
3943 #define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
3944
3945 #define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
3946
3947 #define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
3948
3949 #define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
3950
3951 #define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
3952
3953 #define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
3954
3955 #define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
3956
3957 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
3958
3959 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
3960
3961 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
3962
3963 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
3964
3965 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
3966
3967 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
3968
3969 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
3970
3971 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
3972
3973 #define REG_A4XX_UNKNOWN_2001 0x00002001
3974
3975 #define REG_A4XX_UNKNOWN_209B 0x0000209b
3976
3977 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
3978
3979 #define REG_A4XX_UNKNOWN_2152 0x00002152
3980
3981 #define REG_A4XX_UNKNOWN_2153 0x00002153
3982
3983 #define REG_A4XX_UNKNOWN_2154 0x00002154
3984
3985 #define REG_A4XX_UNKNOWN_2155 0x00002155
3986
3987 #define REG_A4XX_UNKNOWN_2156 0x00002156
3988
3989 #define REG_A4XX_UNKNOWN_2157 0x00002157
3990
3991 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
3992
3993 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
3994
3995 #define REG_A4XX_UNKNOWN_2209 0x00002209
3996
3997 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
3998
3999 #define REG_A4XX_UNKNOWN_2352 0x00002352
4000
4001 #define REG_A4XX_TEX_SAMP_0 0x00000000
4002 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4003 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4004 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)4005 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
4006 {
4007 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
4008 }
4009 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4010 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)4011 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
4012 {
4013 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
4014 }
4015 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4016 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)4017 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
4018 {
4019 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
4020 }
4021 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4022 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)4023 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
4024 {
4025 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
4026 }
4027 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4028 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)4029 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
4030 {
4031 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
4032 }
4033 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4034 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)4035 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
4036 {
4037 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
4038 }
4039 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4040 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
A4XX_TEX_SAMP_0_LOD_BIAS(float val)4041 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
4042 {
4043 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
4044 }
4045
4046 #define REG_A4XX_TEX_SAMP_1 0x00000001
4047 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4048 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)4049 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4050 {
4051 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4052 }
4053 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4054 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4055 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4056 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4057 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
A4XX_TEX_SAMP_1_MAX_LOD(float val)4058 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
4059 {
4060 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
4061 }
4062 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4063 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
A4XX_TEX_SAMP_1_MIN_LOD(float val)4064 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
4065 {
4066 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
4067 }
4068
4069 #define REG_A4XX_TEX_CONST_0 0x00000000
4070 #define A4XX_TEX_CONST_0_TILED 0x00000001
4071 #define A4XX_TEX_CONST_0_SRGB 0x00000004
4072 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4073 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)4074 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
4075 {
4076 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
4077 }
4078 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4079 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)4080 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
4081 {
4082 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
4083 }
4084 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4085 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)4086 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
4087 {
4088 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
4089 }
4090 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4091 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)4092 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
4093 {
4094 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
4095 }
4096 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4097 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)4098 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
4099 {
4100 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
4101 }
4102 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
4103 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)4104 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
4105 {
4106 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
4107 }
4108 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
4109 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)4110 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
4111 {
4112 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
4113 }
4114
4115 #define REG_A4XX_TEX_CONST_1 0x00000001
4116 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
4117 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
A4XX_TEX_CONST_1_HEIGHT(uint32_t val)4118 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
4119 {
4120 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
4121 }
4122 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
4123 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
A4XX_TEX_CONST_1_WIDTH(uint32_t val)4124 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
4125 {
4126 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
4127 }
4128
4129 #define REG_A4XX_TEX_CONST_2 0x00000002
4130 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
4131 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)4132 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
4133 {
4134 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
4135 }
4136 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
4137 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
A4XX_TEX_CONST_2_PITCH(uint32_t val)4138 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
4139 {
4140 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
4141 }
4142 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
4143 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)4144 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
4145 {
4146 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
4147 }
4148
4149 #define REG_A4XX_TEX_CONST_3 0x00000003
4150 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
4151 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)4152 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
4153 {
4154 assert(!(val & 0xfff));
4155 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
4156 }
4157 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
4158 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
A4XX_TEX_CONST_3_DEPTH(uint32_t val)4159 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
4160 {
4161 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
4162 }
4163
4164 #define REG_A4XX_TEX_CONST_4 0x00000004
4165 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
4166 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)4167 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
4168 {
4169 assert(!(val & 0xfff));
4170 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
4171 }
4172 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
4173 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
A4XX_TEX_CONST_4_BASE(uint32_t val)4174 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
4175 {
4176 assert(!(val & 0x1f));
4177 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
4178 }
4179
4180 #define REG_A4XX_TEX_CONST_5 0x00000005
4181
4182 #define REG_A4XX_TEX_CONST_6 0x00000006
4183
4184 #define REG_A4XX_TEX_CONST_7 0x00000007
4185
4186 #define REG_A4XX_SSBO_0_0 0x00000000
4187 #define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0
4188 #define A4XX_SSBO_0_0_BASE__SHIFT 5
A4XX_SSBO_0_0_BASE(uint32_t val)4189 static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
4190 {
4191 assert(!(val & 0x1f));
4192 return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
4193 }
4194
4195 #define REG_A4XX_SSBO_0_1 0x00000001
4196 #define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff
4197 #define A4XX_SSBO_0_1_PITCH__SHIFT 0
A4XX_SSBO_0_1_PITCH(uint32_t val)4198 static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val)
4199 {
4200 return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK;
4201 }
4202
4203 #define REG_A4XX_SSBO_0_2 0x00000002
4204 #define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
4205 #define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)4206 static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
4207 {
4208 assert(!(val & 0xfff));
4209 return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
4210 }
4211
4212 #define REG_A4XX_SSBO_0_3 0x00000003
4213 #define A4XX_SSBO_0_3_CPP__MASK 0x0000003f
4214 #define A4XX_SSBO_0_3_CPP__SHIFT 0
A4XX_SSBO_0_3_CPP(uint32_t val)4215 static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val)
4216 {
4217 return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK;
4218 }
4219
4220 #define REG_A4XX_SSBO_1_0 0x00000000
4221 #define A4XX_SSBO_1_0_CPP__MASK 0x0000001f
4222 #define A4XX_SSBO_1_0_CPP__SHIFT 0
A4XX_SSBO_1_0_CPP(uint32_t val)4223 static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val)
4224 {
4225 return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK;
4226 }
4227 #define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00
4228 #define A4XX_SSBO_1_0_FMT__SHIFT 8
A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)4229 static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)
4230 {
4231 return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK;
4232 }
4233 #define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000
4234 #define A4XX_SSBO_1_0_WIDTH__SHIFT 16
A4XX_SSBO_1_0_WIDTH(uint32_t val)4235 static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val)
4236 {
4237 return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK;
4238 }
4239
4240 #define REG_A4XX_SSBO_1_1 0x00000001
4241 #define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
4242 #define A4XX_SSBO_1_1_HEIGHT__SHIFT 0
A4XX_SSBO_1_1_HEIGHT(uint32_t val)4243 static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val)
4244 {
4245 return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK;
4246 }
4247 #define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000
4248 #define A4XX_SSBO_1_1_DEPTH__SHIFT 16
A4XX_SSBO_1_1_DEPTH(uint32_t val)4249 static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val)
4250 {
4251 return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK;
4252 }
4253
4254
4255 #endif /* A4XX_XML */
4256