Searched refs:CheckDef (Results 1 – 4 of 4) sorted by relevance
| /external/swiftshader/third_party/SPIRV-Tools/test/opt/ |
| D | def_use_test.cpp | 93 void CheckDef(const InstDefUse& expected_defs_uses, in CheckDef() function
204 CheckDef(tc.du, manager.id_to_defs()); in TEST_P()
627 CheckDef(tc.du, context->get_def_use_mgr()->id_to_defs()); in TEST_P()
979 CheckDef(tc.du, context->get_def_use_mgr()->id_to_defs()); in TEST_P()
1297 CheckDef(def_uses, context->get_def_use_mgr()->id_to_defs()); in TEST()
1340 CheckDef(tc.expected_define_use, manager.id_to_defs()); in TEST_P()
1397 CheckDef(expected, manager.id_to_defs()); in TEST()
1427 CheckDef(expected, manager.id_to_defs()); in TEST()
1461 CheckDef(tc.expected_define_use, context->get_def_use_mgr()->id_to_defs()); in TEST_P()
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| /external/deqp-deps/SPIRV-Tools/test/opt/ |
| D | def_use_test.cpp | 93 void CheckDef(const InstDefUse& expected_defs_uses, in CheckDef() function
204 CheckDef(tc.du, manager.id_to_defs()); in TEST_P()
627 CheckDef(tc.du, context->get_def_use_mgr()->id_to_defs()); in TEST_P()
979 CheckDef(tc.du, context->get_def_use_mgr()->id_to_defs()); in TEST_P()
1297 CheckDef(def_uses, context->get_def_use_mgr()->id_to_defs()); in TEST()
1340 CheckDef(tc.expected_define_use, manager.id_to_defs()); in TEST_P()
1397 CheckDef(expected, manager.id_to_defs()); in TEST()
1427 CheckDef(expected, manager.id_to_defs()); in TEST()
1461 CheckDef(tc.expected_define_use, context->get_def_use_mgr()->id_to_defs()); in TEST_P()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 826 static bool isImplicitDependency(const MachineInstr &I, bool CheckDef, in isImplicitDependency() argument
829 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg)) in isImplicitDependency()
833 if (CheckDef == MO.isDef()) in isImplicitDependency()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | VirtRegRewriter.cpp | 1623 bool CheckDef = PrevMII != MBB->begin(); in SpillRegToStackSlot() local
1624 if (CheckDef) in SpillRegToStackSlot()
1627 if (CheckDef) { in SpillRegToStackSlot()
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