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Searched refs:CoveringLanes (Results 1 – 10 of 10) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h266 unsigned CoveringLanes; variable
274 unsigned CoveringLanes);
408 LaneBitmask getCoveringLanes() const { return CoveringLanes; } in getCoveringLanes()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h235 LaneBitmask CoveringLanes; variable
245 LaneBitmask CoveringLanes,
419 LaneBitmask getCoveringLanes() const { return CoveringLanes; } in getCoveringLanes()
/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp38 CoveringLanes(SRICoveringLanes) { in TargetRegisterInfo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp52 CoveringLanes(SRICoveringLanes), in TargetRegisterInfo()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.h772 LaneBitmask CoveringLanes; variable
DCodeGenRegisters.cpp1365 CoveringLanes = LaneBitmask::getAll(); in computeSubRegLaneMasks()
1467 CoveringLanes &= ~Mask; in computeSubRegLaneMasks()
DRegisterInfoEmitter.cpp1478 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h724 unsigned CoveringLanes; variable
DCodeGenRegisters.cpp1170 CoveringLanes = ~0u; in computeSubRegLaneMasks()
1270 CoveringLanes &= ~Mask; in computeSubRegLaneMasks()
DRegisterInfoEmitter.cpp1434 OS.write_hex(RegBank.CoveringLanes); in runTargetDesc()