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Searched refs:Cycles (Results 1 – 25 of 129) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86PadShortFunction.cpp42 unsigned int Cycles; member
44 VisitedBBInfo() : HasReturn(false), Cycles(0) {} in VisitedBBInfo()
45 VisitedBBInfo(bool HasReturn, unsigned int Cycles) in VisitedBBInfo()
46 : HasReturn(HasReturn), Cycles(Cycles) {} in VisitedBBInfo()
67 unsigned int Cycles = 0);
70 unsigned int &Cycles);
117 unsigned int Cycles = 0; in runOnMachineFunction() local
123 Cycles = I->second; in runOnMachineFunction()
125 if (Cycles < Threshold) { in runOnMachineFunction()
137 addPadding(MBB, ReturnLoc, Threshold - Cycles); in runOnMachineFunction()
[all …]
/external/llvm/lib/Target/X86/
DX86PadShortFunction.cpp44 unsigned int Cycles; member
46 VisitedBBInfo() : HasReturn(false), Cycles(0) {} in VisitedBBInfo()
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles) in VisitedBBInfo()
48 : HasReturn(HasReturn), Cycles(Cycles) {} in VisitedBBInfo()
69 unsigned int Cycles = 0);
72 unsigned int &Cycles);
122 unsigned int Cycles = 0; in runOnMachineFunction() local
128 Cycles = I->second; in runOnMachineFunction()
130 if (Cycles < Threshold) { in runOnMachineFunction()
142 addPadding(MBB, ReturnLoc, Threshold - Cycles); in runOnMachineFunction()
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/external/llvm/include/llvm/MC/
DMCSchedule.h57 unsigned Cycles; member
60 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
70 int Cycles; member
74 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
89 int Cycles; member
93 && Cycles == Other.Cycles;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCSchedule.h66 uint16_t Cycles; member
69 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
79 int16_t Cycles; member
83 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
98 int Cycles; member
102 && Cycles == Other.Cycles;
/external/dagger2/compiler/src/it/functional-tests/src/test/java/test/cycle/
DCycleTest.java21 import test.cycle.Cycles.A;
22 import test.cycle.Cycles.C;
23 import test.cycle.Cycles.ChildCycleComponent;
24 import test.cycle.Cycles.CycleComponent;
25 import test.cycle.Cycles.CycleMapComponent;
26 import test.cycle.Cycles.S;
27 import test.cycle.Cycles.SelfCycleComponent;
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DInstructionTables.cpp34 double Cycles = static_cast<double>(Resource.second.size()); in execute() local
41 Cycles /= NumUnits; in execute()
44 UsedResources.emplace_back(std::make_pair(ResourceUnit, Cycles)); in execute()
56 double RUCycles = Cycles / (NumUnits * SubUnit.NumUnits); in execute()
DPipeline.cpp65 ++Cycles; in run()
89 LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycles << '\n'); in notifyCycleBegin()
95 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n\n"); in notifyCycleEnd()
DInstruction.h187 void writeStartEvent(unsigned Cycles);
227 void Subtract(unsigned Cycles) { in Subtract() argument
228 assert(End >= Cycles); in Subtract()
229 End -= Cycles; in Subtract()
247 ResourceUsage(CycleSegment Cycles, unsigned Units = 1)
248 : CS(Cycles), NumUnits(Units) {} in CS()
DTimelineView.h169 unsigned Cycles) in TimelineView() argument
171 MaxCycle(Cycles == 0 ? 80 : Cycles), LastCycle(0) { in TimelineView()
DPipeline.h60 unsigned Cycles; variable
72 Pipeline() : Cycles(0) {} in Pipeline()
DInstrBuilder.cpp57 CycleSegment RCy(0, PRE->Cycles, false); in initializeUsedResources()
61 SuperResources[Super] += PRE->Cycles; in initializeUsedResources()
202 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles); in populateWrites()
233 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles); in populateWrites()
DTimelineView.cpp180 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) { in printTimelineHeader() argument
182 if (Cycles >= 10) { in printTimelineHeader()
184 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
195 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/
DMCSchedule.cpp50 if (WLEntry->Cycles < 0) in computeInstrLatency()
51 return WLEntry->Cycles; in computeInstrLatency()
52 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles)); in computeInstrLatency()
96 if (!I->Cycles) in getReciprocalThroughput()
99 double Temp = NumUnits * 1.0 / I->Cycles; in getReciprocalThroughput()
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/
Dvariable-blend-read-after-ld-1.s22 # BDWELL-NEXT: Total Cycles: 10
27 # BTVER2-NEXT: Total Cycles: 11
32 # HASWELL-NEXT: Total Cycles: 11
37 # IVY-NEXT: Total Cycles: 11
42 # SANDY-NEXT: Total Cycles: 11
47 # SKYLAKE-NEXT: Total Cycles: 11
52 # ZNVER1-NEXT: Total Cycles: 11
Dvariable-blend-read-after-ld-2.s22 # BDWELL-NEXT: Total Cycles: 10
27 # BTVER2-NEXT: Total Cycles: 11
32 # HASWELL-NEXT: Total Cycles: 11
37 # IVY-NEXT: Total Cycles: 11
42 # SANDY-NEXT: Total Cycles: 11
47 # SKYLAKE-NEXT: Total Cycles: 11
52 # ZNVER1-NEXT: Total Cycles: 11
Dfma3-read-after-ld-2.s16 # BDWELL-NEXT: Total Cycles: 13
20 # HASWELL-NEXT: Total Cycles: 14
24 # SKYLAKE-NEXT: Total Cycles: 13
28 # ZNVER1-NEXT: Total Cycles: 15
Dfma3-read-after-ld-1.s16 # BDWELL-NEXT: Total Cycles: 13
20 # HASWELL-NEXT: Total Cycles: 14
24 # SKYLAKE-NEXT: Total Cycles: 13
28 # ZNVER1-NEXT: Total Cycles: 15
Dbextr-read-after-ld.s14 # BDWELL-NEXT: Total Cycles: 10
19 # BTVER2-NEXT: Total Cycles: 7
24 # HASWELL-NEXT: Total Cycles: 10
29 # SKYLAKE-NEXT: Total Cycles: 10
34 # ZNVER1-NEXT: Total Cycles: 8
Dbzhi-read-after-ld.s13 # BDWELL-NEXT: Total Cycles: 9
18 # HASWELL-NEXT: Total Cycles: 9
23 # SKYLAKE-NEXT: Total Cycles: 9
28 # ZNVER1-NEXT: Total Cycles: 8
Dllvm-mca-markers-5.s20 # CHECK-NEXT: Total Cycles: 4
40 # CHECK-NEXT: Total Cycles: 4
60 # CHECK-NEXT: Total Cycles: 4
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp97 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
288 int Cycles = Stage->getValueAsInt("Cycles"); in FormItineraryStageString() local
289 ItinString += " { " + itostr(Cycles) + ", "; in FormItineraryStageString()
754 std::vector<int64_t> &Cycles, in ExpandProcResources() argument
757 Cycles.resize(PRVec.size(), 1); in ExpandProcResources()
776 Cycles.push_back(Cycles[i]); in ExpandProcResources()
793 Cycles.push_back(Cycles[i]); in ExpandProcResources()
900 WLEntry.Cycles = 0; in GenSchedClassTables()
921 WLEntry.Cycles += WriteRes->getValueAsInt("Latency"); in GenSchedClassTables()
928 std::vector<int64_t> Cycles = in GenSchedClassTables() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DSubtargetEmitter.cpp108 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
282 int Cycles = Stage->getValueAsInt("Cycles"); in FormItineraryStageString() local
283 ItinString += " { " + itostr(Cycles) + ", "; in FormItineraryStageString()
942 std::vector<int64_t> &Cycles, in ExpandProcResources() argument
944 assert(PRVec.size() == Cycles.size() && "failed precondition"); in ExpandProcResources()
964 Cycles.push_back(Cycles[i]); in ExpandProcResources()
980 Cycles.push_back(Cycles[i]); in ExpandProcResources()
1080 WLEntry.Cycles = 0; in GenSchedClassTables()
1101 WLEntry.Cycles += WriteRes->getValueAsInt("Latency"); in GenSchedClassTables()
1110 std::vector<int64_t> Cycles = in GenSchedClassTables() local
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/external/llvm/lib/CodeGen/
DTargetSchedule.cpp95 static unsigned capLatency(int Cycles) { in capLatency() argument
96 return Cycles >= 0 ? Cycles : 1000; in capLatency()
194 unsigned Latency = capLatency(WLEntry->Cycles); in computeOperandLatency()
233 Latency = std::max(Latency, capLatency(WLEntry->Cycles)); in computeInstrLatency()
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DAnalysis.cpp346 Result.push_back({WPR->ProcResourceIdx, WPR->Cycles}); in getNonRedundantWriteProcRes()
347 ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles; in getNonRedundantWriteProcRes()
351 float RemainingCycles = WPR->Cycles; in getNonRedundantWriteProcRes()
418 std::max<double>(SchedClassPoint[0].Value, WLE->Cycles); in measurementsMatch()
468 OS << "<li>" << Entry->Cycles; in printSchedClassDescHtml()
482 OS << "</span>: " << WPR.Cycles << "</li>"; in printSchedClassDescHtml()
735 DensePressure[WPR.ProcResourceIdx] += WPR.Cycles; in computeIdealizedProcResPressure()
741 distributePressure(WPR.Cycles, Subunits, DensePressure); in computeIdealizedProcResPressure()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetSchedule.cpp127 static unsigned capLatency(int Cycles) { in capLatency() argument
128 return Cycles >= 0 ? Cycles : 1000; in capLatency()
225 unsigned Latency = capLatency(WLEntry->Cycles); in computeOperandLatency()

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