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/external/libusb/msvc/
Dlibusb_2005.sln4 …2}") = "libusb-1.0 (static)", "libusb_static_2005.vcproj", "{5AB6B770-1925-48D5-ABC2-930F3259C020}"
16 …8D11-00A0C91BC942}") = "listdevs", "listdevs_2005.vcproj", "{98CFD8FA-EE20-40D5-AF13-F8C4856D6CA5}"
22 {5AB6B770-1925-48D5-ABC2-930F3259C020} = {5AB6B770-1925-48D5-ABC2-930F3259C020}
31 {5AB6B770-1925-48D5-ABC2-930F3259C020} = {5AB6B770-1925-48D5-ABC2-930F3259C020}
40 {5AB6B770-1925-48D5-ABC2-930F3259C020} = {5AB6B770-1925-48D5-ABC2-930F3259C020}
51 {5AB6B770-1925-48D5-ABC2-930F3259C020}.Debug|Win32.ActiveCfg = Debug|Win32
52 {5AB6B770-1925-48D5-ABC2-930F3259C020}.Debug|Win32.Build.0 = Debug|Win32
53 {5AB6B770-1925-48D5-ABC2-930F3259C020}.Debug|x64.ActiveCfg = Debug|x64
54 {5AB6B770-1925-48D5-ABC2-930F3259C020}.Debug|x64.Build.0 = Debug|x64
55 {5AB6B770-1925-48D5-ABC2-930F3259C020}.Release|Win32.ActiveCfg = Release|Win32
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/external/libxaac/decoder/armv7/
Dixheaacd_dec_DCT2_64_asm.s89 VSWP D4, D5
122 VSWP D4, D5
166 VSWP D4, D5
216 VSWP D4, D5
331 VLD2.16 {D4, D5}, [R7]!
338 VMLSL.U16 Q14, D2, D5
341 VMLSL.S16 Q14, D3, D5
344 VMULL.U16 Q13, D0, D5
347 VMLAL.S16 Q13, D1, D5
359 VLD2.16 {D4, D5}, [R7]!
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Dixheaacd_esbr_qmfsyn64_winadd.s54 VLD1.32 {D4, D5}, [R0], R8
58 VMLAL.S32 Q14, D7, D5
90 VLD1.32 {D4, D5}, [R1], R8
96 VMLAL.S32 Q14, D7, D5
147 VLD1.32 {D4, D5}, [R0], R8
151 VMLAL.S32 Q14, D7, D5
183 VLD1.32 {D4, D5}, [R1], R8
189 VMLAL.S32 Q14, D7, D5
233 VLD1.32 {D4, D5}, [R0], R8
240 VMLAL.S32 Q14, D7, D5
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Dixheaacd_dct3_32.s67 VUZP.16 D4, D5
97 VMLAL.S16 Q15, D5, D12
102 VMLAL.S16 Q14, D5, D13
106 VUZP.16 D4, D5
146 VMLAL.S16 Q14, D5, D13
150 VMLAL.S16 Q15, D5, D12
162 VUZP.16 D4, D5
183 VMLAL.S16 Q15, D5, D12
196 VMLAL.S16 Q14, D5, D13
216 VUZP.16 D4, D5
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Dixheaacd_overlap_add1.s71 VLD1.32 {D4, D5}, [R1]!
82 VMULL.S32 Q13, D5, D15
103 VMULL.S32 Q0, D15, D5
118 VLD1.32 {D4, D5}, [R1]!
147 VMULL.S32 Q8, D5, D15
157 VMULL.S32 Q0, D5, D15
162 VLD1.32 {D4, D5}, [R1]!
197 VMULL.S32 Q8, D5, D15
207 VMULL.S32 Q0, D5, D15
222 VLD1.32 {D4, D5}, [R1]!
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Dixheaacd_pre_twiddle_compute.s114 VLD4.16 {D4, D5, D6, D7}, [R1], R8
135 VMLAL.S16 Q14, D5, D9
137 VMLAL.S16 Q12, D5, D8
176 VLD4.16 {D4, D5, D6, D7}, [R1], R8
204 VMLAL.S16 Q14, D5, D9
206 VMLAL.S16 Q12, D5, D8
240 VLD4.16 {D4, D5, D6, D7}, [R1], R8
268 VMLAL.S16 Q14, D5, D9
270 VMLAL.S16 Q12, D5, D8
321 VLD2.32 {D5, D7}, [R1]!
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Dixheaacd_post_twiddle.s103 VLD4.16 {D4, D5, D6, D7}, [R1]!
152 VMLAL.S16 Q10, D5, D9
154 VMLAL.S16 Q8, D5, D8
207 VLD4.16 {D4, D5, D6, D7}, [R1]!
260 VMLAL.S16 Q10, D5, D9
262 VMLAL.S16 Q8, D5, D8
313 VLD4.16 {D4, D5, D6, D7}, [R1]!
368 VMLAL.S16 Q10, D5, D9
370 VMLAL.S16 Q8, D5, D8
424 VMOV.S32 D5, #0x00000000
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Dixheaacd_overlap_add2.s57 VREV64.16 D5, D7
69 VMLSL.S16 Q13, D5, D3
87 VREV64.16 D5, D7
98 VMLSL.S16 Q13, D5, D3
169 VLD2.16 {D4, D5}, [R1]!
175 VMLSL.S16 Q13, D5, D2
193 VMLSL.S16 Q13, D5, D2
215 VLD2.16 {D4, D5}, [R1]!
230 VMLSL.S16 Q13, D5, D2
Dixheaacd_sbr_qmfsyn64_winadd.s71 VLD1.16 D5, [R2], R9
74 VMLAL.S16 Q13, D5, D4
145 VLD1.16 D5, [R2], R9
190 VMLAL.S16 Q13, D5, D4
218 VLD1.16 D5, [R2], R9
233 VMLAL.S16 Q13, D5, D4
298 VLD1.16 D5, [R2], R9
347 VMLAL.S16 Q13, D5, D4
Dixheaacd_calc_pre_twid.s39 VLD2.32 {D4, D5}, [R0]!
46 VNEG.S32 D5, D4
49 VMULL.S32 Q6, D0, D5
Dixheaacd_calc_post_twid.s40 VLD1.32 {D4, D5}, [R1]!
47 VMULL.S32 Q8, D5, D1
50 VMULL.S32 Q11, D5, D3
Dixheaacd_sbr_qmfanal32_winadds.s98 VLD2.16 {D5, D6}, [R2]!
103 VMLAL.S16 Q15, D4, D5
190 VLD2.16 {D5, D6}, [R2]!
197 VMLAL.S16 Q15, D4, D5
Dixheaacd_mps_synt_post_fft_twiddle.s40 VLD1.32 {D4, D5}, [R3]!
45 VMULL.S32 Q6, D1, D5
/external/libhevc/common/arm/
Dihevc_resi_trans_32x32_a9q.s165 VLD1.U8 {D4,D5},[R1]! @LOAD 1-16 pred row 1
172 VSUBL.U8 Q9,D1,D5 @ Get residue 9-16 row 1 -- dual issue
188 VABAL.U8 Q15,D1,D5
211 VSWP D4,D5 @ Q2: 24 23 22 21 20 19 18 17 row 2
232 VREV64.S16 D9,D5 @ rev ee[k] k-> 4-7 row 2
256 VNEG.S16 D5,D4
267 VTRN.S16 D4,D5
273 VDUP.S32 D10,D5[0] @ R1eeee[1] R1eeeo[1] R1eeee[1] R1eeeo[1]
274 VDUP.S32 D11,D5[1] @ R2eeee[1] R2eeeo[1] R2eeee[1] R2eeeo[1]
277 @D5 : [0 1] [8 1] [16 1] [24 1]
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Dihevc_sao_band_offset_chroma.s133 …VADD.I8 D5,D1,D31 @band_table_u.val[0] = vadd_u8(band_table_u.val[0], sao_ba…
151 …VADD.I8 D1,D5,D29 @band_table_u.val[0] = vadd_u8(band_table_u.val[0], vdup_n…
295 VLD2.8 {D5,D6},[r4] @vld1q_u8(pu1_src_cpy)
299 VSUB.I8 D7,D5,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
307 …VTBX.8 D5,{D1-D4},D7 @vtbx4_u8(au1_cur_row_deint.val[0], band_table_u, vsub_u8(…
319 VST2.8 {D5,D6},[r4] @vst1q_u8(pu1_src_cpy, au1_cur_row)
348 VLD2.8 {D5,D6},[r4] @vld1q_u8(pu1_src_cpy)
353 VSUB.I8 D7,D5,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
358 …VTBX.8 D5,{D1-D4},D7 @vtbx4_u8(au1_cur_row_deint.val[0], band_table_u, vsub_u8(…
371 VZIP.8 D5,D6
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/external/clang/test/CodeGenCXX/
Dhomogeneous-aggregates.cpp39 struct D5 : I1, I2, I3 {}; // homogeneous aggregate struct
63 D5 CC func_D5(D5 x) { return x; } in func_D5()
74 void call_D5(D5 *p) { in call_D5()
/external/libpng/projects/vstudio/
Dvstudio.sln13 …-8D11-00A0C91BC942}") = "pngtest", "pngtest\pngtest.vcxproj", "{228BA965-50D5-42B2-8BCF-AFCC227E3C…
57 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Debug Library|Win32.ActiveCfg = Debug Library|Win32
58 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Debug Library|Win32.Build.0 = Debug Library|Win32
59 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Debug|Win32.ActiveCfg = Debug|Win32
60 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Debug|Win32.Build.0 = Debug|Win32
61 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Release Library|Win32.ActiveCfg = Release Library|Win32
62 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Release Library|Win32.Build.0 = Release Library|Win32
63 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Release|Win32.ActiveCfg = Release|Win32
64 {228BA965-50D5-42B2-8BCF-AFCC227E3C1D}.Release|Win32.Build.0 = Release|Win32
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/Support/
DAlignOfTest.cpp57 struct D5 : S3 { char c; }; argument
60 struct D8 : S1, D4, D5 { double x[2]; };
154 EXPECT_EQ(alignof(D5), alignof(AlignedCharArrayUnion<D5>)); in TEST()
209 EXPECT_EQ(sizeof(D5), sizeof(AlignedCharArrayUnion<D5>)); in TEST()
/external/llvm/unittests/Support/
DAlignOfTest.cpp57 struct D5 : S3 { char c; }; struct
60 struct D8 : S1, D4, D5 { double x[2]; };
139 [AlignOf<D5>::Alignment > 0]
180 EXPECT_LE(alignOf<S1>(), alignOf<D5>()); in TEST()
262 EXPECT_EQ(alignOf<D5>(), alignOf<AlignedCharArrayUnion<D5> >()); in TEST()
317 EXPECT_EQ(sizeof(D5), sizeof(AlignedCharArrayUnion<D5>)); in TEST()
/external/curl/tests/data/
Dtest153734 %2F%3A%3B%3C%3D%3E%3F%91%A2%B3%C4%D5%E6%F7
35 %2F%3A%3B%3C%3D%3E%3F%91%A2%B3%C4%D5%E6%F7
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DConcatenatedSubregs.td56 def D5 : MyReg<"d5", [S10, S11]>;
88 // CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14
115 // CHECK-NEXT: SubReg ssub1_ssub2 = D5
126 // CHECK-NEXT: SubReg sub0 = D5
/external/boringssl/src/crypto/chacha/asm/
Dchacha-armv8.pl693 $A3,$B3,$C3,$D3,$A4,$B4,$C4,$D4,$A5,$B5,$C5,$D5) = map("v$_.4s",(0..23));
779 add $D5,$D1,$ONE // +4
800 my @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,0);
819 @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,1);
914 @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,0);
931 @thread5=&NEONROUND($A5,$B5,$C5,$D5,$T5,1);
978 add $D5,$D5,$ONE // +4
990 add $D5,$D5,@K[4]
1071 eor $D5,$D5,$D3
1072 st1.8 {$A5-$D5},[$out],#64
/external/llvm/test/CodeGen/AArch64/
Dfp16-v16-instructions.ll29 ; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
40 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
80 ; CHECK-DAG: ucvtf [[D5:v[0-9]+\.2d]], v5.2d
91 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dfp16-v16-instructions.ll29 ; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
40 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
80 ; CHECK-DAG: ucvtf [[D5:v[0-9]+\.2d]], v5.2d
91 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
/external/toybox/tests/files/bc/
Dparse.txt12069 D5
12070 0.D5
12071 1.D5
12072 D5.D5
13150 D5
13151 0.D5
13152 1.D5
13153 D5.D5
14231 D5
14232 0.D5
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