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Searched refs:DCACHE (Results 1 – 8 of 8) sorted by relevance

/external/ltp/testcases/kernel/syscalls/cacheflush/
Dcacheflush01.c56 #ifndef DCACHE
57 #define DCACHE (1<<1) /* writeback and flush data cache */ macro
60 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
141 TEST(ltp_syscall(__NR_cacheflush, addr, getpagesize(), DCACHE)); in main()
/external/u-boot/arch/nds32/lib/
Dcache.c140 line_size = CACHE_LINE_SIZE(DCACHE); in dcache_wbinval_all()
141 end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE); in dcache_wbinval_all()
163 line_size = CACHE_LINE_SIZE(DCACHE); in flush_dcache_range()
178 line_size = CACHE_LINE_SIZE(DCACHE); in invalidate_dcache_range()
/external/kernel-headers/original/uapi/asm-mips/asm/
Dcachectl.h16 #define DCACHE (1<<1) /* writeback and flush data cache */ macro
17 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/external/u-boot/arch/mips/include/asm/
Dcachectl.h12 #define DCACHE (1<<1) /* writeback and flush data cache */ macro
13 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/external/u-boot/arch/arm/cpu/armv7m/
Dcache.c41 DCACHE, enumerator
119 if (type == DCACHE) in get_cline_size()
148 type = DCACHE; in action_cache_range()
/external/u-boot/arch/nds32/include/asm/
Dcache.h30 enum cache_t {ICACHE, DCACHE}; enumerator
/external/strace/
Dcacheflush.c75 XLAT(DCACHE),
/external/u-boot/
DREADME4707 is this: Using DCACHE as initial RAM for Stack, etc, does not