| /external/u-boot/arch/arm/mach-keystone/include/mach/ |
| D | clock-k2hk.h | 38 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
39 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
40 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
41 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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| /external/u-boot/board/freescale/mx6memcal/ |
| D | Kconfig | 88 Select the type of DDR (DDR3 or LPDDR2) used on your design
90 config DDR3 config in mx6memcal specifics""choicee857b7490304
91 bool "DDR3"
93 Select this if your board design uses DDR3.
107 depends on DDR3
111 depends on DDR3
115 depends on DDR3
119 depends on DDR3
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| D | README | 35 4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
38 parts and four DDR3 and two LPDDR2 parts are currently defined
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3368-dmc.txt | 8 (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
19 the DDR3 device's speed-bin (as specified according to JESD-79)
51 Example (for DDR3-1600K and 800MHz)
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | Kconfig | 339 bool "DDR3 1333"
369 Set the dram type, 3: DDR3, 7: LPDDR3
382 (for DDR3-1600) are 312 to 792.
452 Select the timings of the DDR3 chips.
460 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
462 Use the timings of the standard JEDEC DDR3-1066F speed bin for
463 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
464 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
465 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
466 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
[all …]
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| /external/u-boot/drivers/ddr/fsl/ |
| D | Kconfig | 80 Enable Freescale DDR3 controller for PowerPC SoCs.
86 Enable Freescale DDR3 controller for ARM SoCs.
118 bool "Freescale DDR3 controller"
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| /external/u-boot/arch/arm/mach-rockchip/ |
| D | Kconfig | 12 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
71 video interfaces supporting HDMI and eDP, several DDR3 options
91 video interfaces supporting HDMI and eDP, several DDR3 options
111 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
148 video interfaces supporting HDMI and eDP, several DDR3 options
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| /external/u-boot/arch/arm/dts/ |
| D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 10 * DDR type / Platform DDR3/3L
13 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
20 #define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
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| /external/u-boot/board/toradex/colibri_imx6/ |
| D | 800mhz_2x64mx16.cfg | 17 /* DDR3 DATA BUS SIZE: 64BIT */
19 /* DDR3 DATA BUS SIZE: 32BIT */
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| D | 800mhz_4x64mx16.cfg | 17 /* DDR3 DATA BUS SIZE: 64BIT */
19 /* DDR3 DATA BUS SIZE: 32BIT */
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| /external/u-boot/doc/device-tree-bindings/ram/ |
| D | st,stm32mp1-ddr.txt | 1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
175 st,mem-name = "DDR3 2x4Gb 533MHz";
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| /external/u-boot/board/seco/mx6quq7/ |
| D | mx6quq7-2g.cfg | 76 * DDR3 SETTINGS
115 * in DDR3, 64-bit mode, only MMDC0 is init
135 /* Initialize DDR3 on CS_0 and CS_1 */
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| /external/u-boot/board/freescale/p1_p2_rdb_pc/ |
| D | README | 13 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
17 * DDR3
|
| /external/u-boot/board/gdsys/a38x/ |
| D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/CZ.NIC/turris_omnia/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/Marvell/db-88f6820-gp/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/Synology/ds414/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/Marvell/db-88f6720/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/Marvell/db-88f6820-amc/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/solidrun/clearfog/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/theadorable/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/maxbcm/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/Marvell/db-mv784mp-gp/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/kobol/helios4/ |
| D | kwbimage.cfg | 12 # Binary Header (bin_hdr) with DDR3 training code
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| /external/u-boot/drivers/ram/stm32mp1/ |
| D | Kconfig | 10 family: support for LPDDR2, LPDDR3 and DDR3
|