Home
last modified time | relevance | path

Searched refs:DDR_TIMING_CFG_5 (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/include/configs/
Dls1021aiot.h36 #define DDR_TIMING_CFG_5 0x03401400 macro
Dls1021atwr.h37 #define DDR_TIMING_CFG_5 0x03401400 macro
/external/u-boot/board/freescale/ls1021aiot/
Dls1021aiot.c62 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
/external/u-boot/board/freescale/ls1021atwr/
Dls1021atwr.c154 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()