Searched refs:DEBUG_INIT_FULL_S (Results 1 – 8 of 8) sorted by relevance
361 DEBUG_INIT_FULL_S("info->line0_7= 0x"); in serdes_phy_config()363 DEBUG_INIT_FULL_S(" info->line8_15= 0x"); in serdes_phy_config()365 DEBUG_INIT_FULL_S("\n"); in serdes_phy_config()368 DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n"); in serdes_phy_config()396 DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n"); in serdes_phy_config()430 DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n"); in serdes_phy_config()497 DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n"); in serdes_phy_config()514 DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n"); in serdes_phy_config()526 DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n"); in serdes_phy_config()533 DEBUG_INIT_FULL_S("SERDES "); in serdes_phy_config()[all …]
27 DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n"); in hws_pex_config()83 DEBUG_INIT_FULL_S("Support gen1/gen2\n"); in hws_pex_config()92 DEBUG_INIT_FULL_S(" serdes_type=0x"); in hws_pex_config()94 DEBUG_INIT_FULL_S("\n"); in hws_pex_config()95 DEBUG_INIT_FULL_S(" idx=0x"); in hws_pex_config()97 DEBUG_INIT_FULL_S("\n"); in hws_pex_config()135 DEBUG_INIT_FULL_S in hws_pex_config()142 DEBUG_INIT_FULL_S("PCIe, Idx "); in hws_pex_config()231 DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n"); in pex_local_bus_num_set()252 DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n"); in pex_local_dev_num_set()
893 DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n"); in hws_serdes_seq_db_init()1302 DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n"); in serdes_type_and_speed_to_speed_seq()1417 DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n"); in serdes_phy_config()1430 DEBUG_INIT_FULL_S in serdes_phy_config()1443 DEBUG_INIT_FULL_S in serdes_phy_config()1448 DEBUG_INIT_FULL_S in serdes_phy_config()1487 DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n"); in hws_power_up_serdes_lanes()1490 DEBUG_INIT_FULL_S in hws_power_up_serdes_lanes()1496 DEBUG_INIT_FULL_S in hws_power_up_serdes_lanes()1499 DEBUG_INIT_FULL_S("\n"); in hws_power_up_serdes_lanes()[all …]
37 DEBUG_INIT_FULL_S("\n### serdes_seq_init ###\n"); in hws_serdes_seq_init()58 DEBUG_INIT_FULL_S("\n### hws_serdes_silicon_ref_clock_get ###\n"); in hws_serdes_silicon_ref_clock_get()
37 #define DEBUG_INIT_FULL_S(s) puts(s) macro47 #define DEBUG_INIT_FULL_S(s) macro55 { DEBUG_INIT_FULL_S(s); \57 DEBUG_INIT_FULL_S("\n"); }
30 #define DEBUG_INIT_FULL_S(s) puts(s) macro40 #define DEBUG_INIT_FULL_S(s) macro48 { DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); }
719 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Enabled\n");721 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Disabled\n");730 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - R-DIMM\n");732 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - U-DIMM\n");742 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 64Bits\n");744 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");747 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");753 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");755 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
161 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n"); in ddr3_restore_and_set_final_windows()467 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n"); in ddr3_init_main()597 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n"); in ddr3_init_main()610 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n"); in ddr3_init_main()627 DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n"); in ddr3_init_main()633 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n"); in ddr3_init_main()