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Searched refs:DISABLE (Results 1 – 25 of 77) sorted by relevance

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/external/u-boot/board/nvidia/p2571/
Dpinmux-config-p2571.h64 PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
65 PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
66 PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
67 PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
68 PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
69 PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
70 PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
71 PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
72 PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
73 PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
[all …]
/external/u-boot/board/nvidia/p2371-2180/
Dpinmux-config-p2371-2180.h100 PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
101 PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
102 PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
103 PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
104 PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
105 PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
106 PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
107 PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
108 PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
109 PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
[all …]
/external/u-boot/board/nvidia/e2220-1170/
Dpinmux-config-e2220-1170.h98 PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
99 PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL),
100 PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL),
101 PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
102 PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL),
103 PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
104 PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
105 PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
106 PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
107 PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
[all …]
/external/u-boot/board/nvidia/p2371-0000/
Dpinmux-config-p2371-0000.h89 PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
90 PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
91 PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
92 PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
93 PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
94 PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
95 PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
96 PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
97 PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
98 PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
[all …]
/external/u-boot/board/avionic-design/common/
Dpinmux-config-tamonten-ng.h82 LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
83 LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
84 LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
85 LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
86 LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
87 LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
88 LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
89 LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
90 LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
91 LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
[all …]
/external/u-boot/board/nvidia/cardhu/
Dpinmux-config-cardhu.h77 LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
78 LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
79 LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
80 LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
81 LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
82 LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
83 LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
84 LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
85 LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
86 LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
[all …]
/external/u-boot/board/toradex/apalis_t30/
Dpinmux-config-apalis_t30.h79 LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
80 LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
81 LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
82 LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
83 LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
84 LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
85 LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
86 LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
87 LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
88 LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
[all …]
/external/u-boot/board/toradex/colibri_t30/
Dpinmux-config-colibri_t30.h77 LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
78 LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
79 LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
80 LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
81 LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
82 LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
83 LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
84 LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
85 LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
86 LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/
Dthumb-shrink-wrapping.ll6 ; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE --check-prefix=DISABLE-V4T
8 ; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE --check-prefix=DISABLE-V5T
36 ; DISABLE: cmp r0, r1
37 ; DISABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]]
58 ; DISABLE: add sp, #8
59 ; DISABLE-V5T-NEXT: pop {r7, pc}
60 ; DISABLE-V4T-NEXT: pop {r7}
61 ; DISABLE-V4T-NEXT: pop {r1}
62 ; DISABLE-V4T-NEXT: bx r1
95 ; DISABLE: add sp, #8
[all …]
/external/llvm/test/CodeGen/Thumb/
Dthumb-shrink-wrapping.ll6 ; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE --check-prefix=DISABLE-V4T
8 ; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE --check-prefix=DISABLE-V5T
33 ; DISABLE: cmp r0, r1
34 ; DISABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]]
55 ; DISABLE: add sp, #8
56 ; DISABLE-V5T-NEXT: pop {r7, pc}
57 ; DISABLE-V4T-NEXT: pop {r7}
58 ; DISABLE-V4T-NEXT: pop {r1}
59 ; DISABLE-V4T-NEXT: bx r1
92 ; DISABLE: add sp, #8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Ddisable-tail-calls.ll2 …lc < %s -mtriple=arm-unknown-unknown -disable-tail-calls | FileCheck %s --check-prefix=DISABLE-TRUE
3 … -mtriple=arm-unknown-unknown -disable-tail-calls=false | FileCheck %s --check-prefix=DISABLE-FALSE
11 ; DISABLE-FALSE-LABEL: {{\_?}}func_attr
12 ; DISABLE-FALSE: b {{\_?}}callee
14 ; DISABLE-TRUE-LABEL: {{\_?}}func_attr
15 ; DISABLE-TRUE: bl {{\_?}}callee
26 ; DISABLE-FALSE-LABEL: {{\_?}}func_noattr
27 ; DISABLE-FALSE: b {{\_?}}callee
29 ; DISABLE-TRUE-LABEL: {{\_?}}func_noattr
30 ; DISABLE-TRUE: bl {{\_?}}callee
Darm-shrink-wrapping.ll4 …eCheck %s --check-prefix=CHECK --check-prefix=ARM --check-prefix=DISABLE --check-prefix=ARM-DISABLE
8 …ck %s --check-prefix=CHECK --check-prefix=THUMB --check-prefix=DISABLE --check-prefix=THUMB-DISABLE
34 ; DISABLE: sub sp
35 ; DISABLE: cmp r0, r1
36 ; DISABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]]
41 ; DISABLE: str r0, [sp]
57 ; ARM-DISABLE: mov sp, r7
58 ; THUMB-DISABLE: add sp,
59 ; DISABLE-NEXT: pop {r7, pc}
95 ; ARM-DISABLE: cmp r0, #0
[all …]
/external/llvm/test/CodeGen/ARM/
Ddisable-tail-calls.ll2 …lc < %s -mtriple=arm-unknown-unknown -disable-tail-calls | FileCheck %s --check-prefix=DISABLE-TRUE
3 … -mtriple=arm-unknown-unknown -disable-tail-calls=false | FileCheck %s --check-prefix=DISABLE-FALSE
11 ; DISABLE-FALSE-LABEL: {{\_?}}func_attr
12 ; DISABLE-FALSE: b {{\_?}}callee
14 ; DISABLE-TRUE-LABEL: {{\_?}}func_attr
15 ; DISABLE-TRUE: bl {{\_?}}callee
26 ; DISABLE-FALSE-LABEL: {{\_?}}func_noattr
27 ; DISABLE-FALSE: b {{\_?}}callee
29 ; DISABLE-TRUE-LABEL: {{\_?}}func_noattr
30 ; DISABLE-TRUE: bl {{\_?}}callee
Darm-shrink-wrapping.ll4 …eCheck %s --check-prefix=CHECK --check-prefix=ARM --check-prefix=DISABLE --check-prefix=ARM-DISABLE
8 …ck %s --check-prefix=CHECK --check-prefix=THUMB --check-prefix=DISABLE --check-prefix=THUMB-DISABLE
34 ; DISABLE: sub sp
35 ; DISABLE: cmp r0, r1
36 ; DISABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]]
41 ; DISABLE: str r0, [sp]
57 ; ARM-DISABLE: mov sp, r7
58 ; THUMB-DISABLE: add sp,
59 ; DISABLE-NEXT: pop {r7, pc}
95 ; ARM-DISABLE: cmp r0, #0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Ddisable-tail-calls.ll2 ; RUN: llc < %s -mtriple=x86_64-- -disable-tail-calls | FileCheck %s --check-prefix=DISABLE-TRUE
3 ; RUN: llc < %s -mtriple=x86_64-- -disable-tail-calls=false | FileCheck %s --check-prefix=DISABLE-F…
11 ; DISABLE-FALSE-LABEL: {{\_?}}func_attr
12 ; DISABLE-FALSE: jmp {{\_?}}callee
14 ; DISABLE-TRUE-LABEL: {{\_?}}func_attr
15 ; DISABLE-TRUE: callq {{\_?}}callee
26 ; DISABLE-FALSE-LABEL: {{\_?}}func_noattr
27 ; DISABLE-FALSE: jmp {{\_?}}callee
29 ; DISABLE-TRUE-LABEL: {{\_?}}func_noattr
30 ; DISABLE-TRUE: callq {{\_?}}callee
Dcodegen-prepare-extload.ll5 …macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
39 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
40 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
64 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
65 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
102 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
103 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
134 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
135 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
167 ; DISABLE: add nuw i8
[all …]
/external/llvm/test/CodeGen/X86/
Ddisable-tail-calls.ll2 ; RUN: llc < %s -march x86-64 -disable-tail-calls | FileCheck %s --check-prefix=DISABLE-TRUE
3 ; RUN: llc < %s -march x86-64 -disable-tail-calls=false | FileCheck %s --check-prefix=DISABLE-FALSE
11 ; DISABLE-FALSE-LABEL: {{\_?}}func_attr
12 ; DISABLE-FALSE: jmp {{\_?}}callee
14 ; DISABLE-TRUE-LABEL: {{\_?}}func_attr
15 ; DISABLE-TRUE: callq {{\_?}}callee
26 ; DISABLE-FALSE-LABEL: {{\_?}}func_noattr
27 ; DISABLE-FALSE: jmp {{\_?}}callee
29 ; DISABLE-TRUE-LABEL: {{\_?}}func_noattr
30 ; DISABLE-TRUE: callq {{\_?}}callee
Dcodegen-prepare-extload.ll5 …macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
39 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
40 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
64 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
65 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
102 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
103 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
134 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
135 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
167 ; DISABLE: add nuw i8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-codegen-prepare-extload.ll3 …-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=DISABLE
33 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
34 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
58 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
59 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
96 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
97 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
128 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
129 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
161 ; DISABLE: add nuw i8
[all …]
Darm64-shrink-wrapping.ll2 …=false -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
22 ; DISABLE: cmp w0, w1
23 ; DISABLE-NEXT: b.ge [[EXIT_LABEL:LBB[0-9_]+]]
34 ; DISABLE: [[EXIT_LABEL]]:
73 ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
90 ; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]
92 ; DISABLE: [[ELSE_LABEL]]: ; %if.else
94 ; DISABLE: lsl w0, w1, #1
95 ; DISABLE: [[EPILOG_BB]]: ; %if.end
184 ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-codegen-prepare-extload.ll3 …le-ios -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
33 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
34 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
58 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
59 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
96 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
97 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
128 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
129 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
161 ; DISABLE: add nuw i8
[all …]
Darm64-shrink-wrapping.ll2 …=false -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
22 ; DISABLE: cmp w0, w1
23 ; DISABLE-NEXT: b.ge [[EXIT_LABEL:LBB[0-9_]+]]
34 ; DISABLE: [[EXIT_LABEL]]:
73 ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
90 ; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]
92 ; DISABLE: [[ELSE_LABEL]]: ; %if.else
94 ; DISABLE: lsl w0, w1, #1
95 ; DISABLE: [[EPILOG_BB]]: ; %if.end
184 ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dppc-shrink-wrapping.ll2 …x-gnu %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
27 ; DISABLE: cmpw 0, 3, 4
28 ; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
45 ; DISABLE: [[EXIT_LABEL]]:
49 ; DISABLE: mtlr {{[0-9]+}}
50 ; DISABLE-NEXT: blr
85 ; DISABLE: cmplwi 0, 3, 0
86 ; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
104 ; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
106 ; DISABLE: .[[ELSE_LABEL]]: # %if.else
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/BugPoint/
Dnamed-md.ll3 ; RUN-DISABLE: bugpoint -disable-namedmd-remove -load %llvmshlibdir/BugpointPasses%shlibext %s -out…
4 ; RUN-DISABLE: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s
8 ; CHECK-DISABLE: !llvm.dbg.cu = !{![[FIRST:[0-9]+]], ![[SECOND:[0-9]+]],
9 ; CHECK-DISABLE-SAME: ![[THIRD:[0-9]+]], ![[FOURTH:[0-9]+]], ![[FIFTH:[0-9]+]]}
12 ; CHECK-DISABLE: !named
/external/llvm/test/BugPoint/
Dnamed-md.ll3 ; RUN-DISABLE: bugpoint -disable-namedmd-remove -load %llvmshlibdir/BugpointPasses%shlibext %s -out…
4 ; RUN-DISABLE: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s
8 ; CHECK-DISABLE: !llvm.dbg.cu = !{![[FIRST:[0-9]+]], ![[SECOND:[0-9]+]],
9 ; CHECK-DISABLE-SAME: ![[THIRD:[0-9]+]], ![[FOURTH:[0-9]+]], ![[FIFTH:[0-9]+]]}
12 ; CHECK-DISABLE: !named

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