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Searched refs:DIV_TO_RATE (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3328.c30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
355 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_i2c_get_clk()
399 return DIV_TO_RATE(GPLL_HZ, src_clk_div); in rk3328_i2c_set_clk()
434 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
461 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3328_mmc_get_clk()
463 return DIV_TO_RATE(GPLL_HZ, div) / 2; in rk3328_mmc_get_clk()
512 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_pwm_get_clk()
524 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_pwm_set_clk()
535 return DIV_TO_RATE(OSC_HZ, div); in rk3328_saradc_get_clk()
Dclk_rv1108.c27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
108 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
129 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
140 return DIV_TO_RATE(OSC_HZ, div); in rv1108_saradc_get_clk()
Dclk_rk3128.c27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
304 return DIV_TO_RATE(src_rate, div); in rockchip_mmc_get_clk()
364 return DIV_TO_RATE(PERI_ACLK_HZ, div); in rk3128_peri_get_pclk()
388 return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div); in rk3128_peri_set_pclk()
399 return DIV_TO_RATE(OSC_HZ, div); in rk3128_saradc_get_clk()
478 return DIV_TO_RATE(parent, div); in rk3128_vop_get_rate()
Dclk_rk3399.c42 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
489 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_i2c_get_clk()
588 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_spi_get_clk()
684 return DIV_TO_RATE(OSC_HZ, div); in rk3399_mmc_get_clk()
686 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_mmc_get_clk()
813 return DIV_TO_RATE(OSC_HZ, div); in rk3399_saradc_get_clk()
1197 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_i2c_get_pmuclk()
1226 return DIV_TO_RATE(PPLL_HZ, src_clk_div); in rk3399_i2c_set_pmuclk()
1237 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_pwm_get_clk()
Dclk_rk3368.c41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
192 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
345 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
397 return DIV_TO_RATE(GPLL_HZ, div); in rk3368_spi_get_clk()
435 return DIV_TO_RATE(OSC_HZ, div); in rk3368_saradc_get_clk()
Dclk_rk3288.c130 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
329 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
556 return DIV_TO_RATE(src_rate, div); in rockchip_mmc_get_clk()
636 return DIV_TO_RATE(gclk_rate, div); in rockchip_spi_get_clk()
681 return DIV_TO_RATE(OSC_HZ, div); in rockchip_saradc_get_clk()
Dclk_rk322x.c26 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
236 return DIV_TO_RATE(src_rate, div) / 2; in rockchip_mmc_get_clk()
268 return DIV_TO_RATE(pll_rate, div); in rk322x_mac_set_clk()
Dclk_rk3188.c71 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
284 return DIV_TO_RATE(gclk_rate, div) / 2; in rockchip_mmc_get_clk()
342 return DIV_TO_RATE(gclk_rate, div); in rockchip_spi_get_clk()
Dclk_rk3036.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
235 return DIV_TO_RATE(src_rate, div) / 2; in rockchip_mmc_get_clk()