Searched refs:DLGR (Results 1 – 12 of 12) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | cond-move-05.mir | 69 %3:gr128bit = DLGR %3, %0
|
| D | int-div-05.ll | 170 ; Check that divisions of spilled values can use DLG rather than DLGR.
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-div-05.ll | 170 ; Check that divisions of spilled values can use DLG rather than DLGR.
|
| /external/v8/src/s390/ |
| D | simulator-s390.h | 924 EVALUATE(DLGR);
|
| D | constants-s390.h | 1417 V(dlgr, DLGR, 0xB987) /* type = RRE DIVIDE LOGICAL (64<-128) */ \
|
| D | simulator-s390.cc | 1212 EvalTable[DLGR] = &Simulator::Evaluate_DLGR; in EvalTableInit()
7158 EVALUATE(DLGR) { in EVALUATE() argument
7159 DCHECK_OPCODE(DLGR); in EVALUATE()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1321 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>;
1346 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>;
|
| D | SystemZScheduleZ13.td | 482 def : InstRW<[WLat30, FXa4, GroupAlone], (instregex "DLGR$")>;
|
| D | SystemZScheduleZ14.td | 491 def : InstRW<[WLat30, FXa4, GroupAlone], (instregex "DLGR$")>;
|
| /external/capstone/arch/SystemZ/ |
| D | SystemZGenAsmWriter.inc | 534 1056208U, // DLGR
|
| D | SystemZGenDisassemblerTables.inc | 656 /* 2485 */ MCD_OPC_Decode, 129, 4, 82, // Opcode: DLGR
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1196 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
|