| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 449 DMFC1 = 1, enumerator
790 return Latency::DMFC1 + UsdLatency(); in Usdc1Latency()
1024 Latency::DMFC1 + 1 + XorLatency() + Latency::DMTC1; in NegdLatency()
1033 return Latency::DMFC1 + 1 + Latency::BRANCH + Latency::MOV_D + 4 + in Float64RoundLatency()
1034 Latency::DMFC1 + Latency::BRANCH + Latency::CVT_D_L + 2 + in Float64RoundLatency()
1068 Latency::DMFC1 + Latency::MOV_D; in Float64MaxLatency()
1090 Latency::DMFC1 + Latency::MOV_D; in Float64MinLatency()
1095 int latency = Latency::TRUNC_L_S + Latency::DMFC1; in TruncLSLatency()
1103 int latency = Latency::TRUNC_L_D + Latency::DMFC1; in TruncLDLatency()
1114 3 * Latency::DMFC1 + OrLatency() + Latency::MTC1 + Latency::MOV_S + in TruncUlSLatency()
[all …]
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| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 421 DMFC1 = 1, enumerator
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 153 Opc = Mips::DMFC1; in copyPhysReg()
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| D | MipsInstrFPU.td | 389 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 616 DMFC1 = ((0U << 3) + 1) << 21, enumerator
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| D | disasm-mips64.cc | 1366 case DMFC1: in DecodeTypeRegisterCOP1()
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| D | assembler-mips64.cc | 3013 GenInstrRegister(COP1, DMFC1, rt, fs, f0); in dmfc1()
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| D | simulator-mips64.cc | 3559 case DMFC1: in DecodeTypeRegisterCOP1()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 158 Opc = Mips::DMFC1; in copyPhysReg()
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| D | MipsInstrFPU.td | 517 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
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| D | MipsSEISelLowering.cpp | 3649 ? Mips::DMFC1 in emitFPROUND_PSEUDO()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 578 16443U, // DMFC1
2292 0U, // DMFC1
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| D | MipsGenDisassemblerTables.inc | 803 /* 1587 */ MCD_OPC_Decode, 177, 4, 61, // Opcode: DMFC1
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1216 UINT64_C(1142947840), // DMFC1
5688 case Mips::DMFC1:
8942 …HasStdEnc | Feature_HasMips3 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // DMFC1 = 1203
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| D | MipsGenAsmWriter.inc | 2431 16488U, // DMFC1
5062 0U, // DMFC1
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| D | MipsGenFastISel.inc | 110 return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
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| D | MipsGenInstrInfo.inc | 1218 DMFC1 = 1203,
5263 …LL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1203 = DMFC1
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| D | MipsGenGlobalISel.inc | 2846 …// (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] …
2847 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
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| D | MipsGenDisassemblerTables.inc | 3260 /* 2369 */ MCD::OPC_Decode, 179, 9, 195, 1, // Opcode: DMFC1
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| D | MipsGenAsmMatcher.inc | 5994 …{ 3306 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Featur…
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| D | MipsGenDAGISel.inc | 25187 /* 46810*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMFC1), 0,
25190 // Dst: (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
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