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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
4  * 370/XP, Dove, Orion5x and MV78xx0)
5  *
6  * Ported from the Barebox version to U-Boot by:
7  * Stefan Roese <sr@denx.de>
8  *
9  * The Barebox version is:
10  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
11  *
12  * based on mbus driver from Linux
13  *   (C) Copyright 2008 Marvell Semiconductor
14  *
15  * The Marvell EBU SoCs have a configurable physical address space:
16  * the physical address at which certain devices (PCIe, NOR, NAND,
17  * etc.) sit can be configured. The configuration takes place through
18  * two sets of registers:
19  *
20  * - One to configure the access of the CPU to the devices. Depending
21  *   on the families, there are between 8 and 20 configurable windows,
22  *   each can be use to create a physical memory window that maps to a
23  *   specific device. Devices are identified by a tuple (target,
24  *   attribute).
25  *
26  * - One to configure the access to the CPU to the SDRAM. There are
27  *   either 2 (for Dove) or 4 (for other families) windows to map the
28  *   SDRAM into the physical address space.
29  *
30  * This driver:
31  *
32  * - Reads out the SDRAM address decoding windows at initialization
33  *   time, and fills the mbus_dram_info structure with these
34  *   informations. The exported function mv_mbus_dram_info() allow
35  *   device drivers to get those informations related to the SDRAM
36  *   address decoding windows. This is because devices also have their
37  *   own windows (configured through registers that are part of each
38  *   device register space), and therefore the drivers for Marvell
39  *   devices have to configure those device -> SDRAM windows to ensure
40  *   that DMA works properly.
41  *
42  * - Provides an API for platform code or device drivers to
43  *   dynamically add or remove address decoding windows for the CPU ->
44  *   device accesses. This API is mvebu_mbus_add_window_by_id(),
45  *   mvebu_mbus_add_window_remap_by_id() and
46  *   mvebu_mbus_del_window().
47  */
48 
49 #include <common.h>
50 #include <linux/errno.h>
51 #include <asm/io.h>
52 #include <asm/arch/cpu.h>
53 #include <asm/arch/soc.h>
54 #include <linux/log2.h>
55 #include <linux/mbus.h>
56 
57 /* DDR target is the same on all platforms */
58 #define TARGET_DDR		0
59 
60 /* CPU Address Decode Windows registers */
61 #define WIN_CTRL_OFF		0x0000
62 #define   WIN_CTRL_ENABLE       BIT(0)
63 #define   WIN_CTRL_TGT_MASK     0xf0
64 #define   WIN_CTRL_TGT_SHIFT    4
65 #define   WIN_CTRL_ATTR_MASK    0xff00
66 #define   WIN_CTRL_ATTR_SHIFT   8
67 #define   WIN_CTRL_SIZE_MASK    0xffff0000
68 #define   WIN_CTRL_SIZE_SHIFT   16
69 #define WIN_BASE_OFF		0x0004
70 #define   WIN_BASE_LOW          0xffff0000
71 #define   WIN_BASE_HIGH         0xf
72 #define WIN_REMAP_LO_OFF	0x0008
73 #define   WIN_REMAP_LOW         0xffff0000
74 #define WIN_REMAP_HI_OFF	0x000c
75 
76 #define ATTR_HW_COHERENCY	(0x1 << 4)
77 
78 #define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
79 #define  DDR_BASE_CS_HIGH_MASK  0xf
80 #define  DDR_BASE_CS_LOW_MASK   0xff000000
81 #define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
82 #define  DDR_SIZE_ENABLED       BIT(0)
83 #define  DDR_SIZE_CS_MASK       0x1c
84 #define  DDR_SIZE_CS_SHIFT      2
85 #define  DDR_SIZE_MASK          0xff000000
86 
87 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
88 
89 struct mvebu_mbus_state;
90 
91 struct mvebu_mbus_soc_data {
92 	unsigned int num_wins;
93 	unsigned int num_remappable_wins;
94 	unsigned int (*win_cfg_offset)(const int win);
95 	void (*setup_cpu_target)(struct mvebu_mbus_state *s);
96 };
97 
98 struct mvebu_mbus_state mbus_state
99 	__attribute__ ((section(".data")));
100 static struct mbus_dram_target_info mbus_dram_info
101 	__attribute__ ((section(".data")));
102 
103 /*
104  * Functions to manipulate the address decoding windows
105  */
106 
mvebu_mbus_read_window(struct mvebu_mbus_state * mbus,int win,int * enabled,u64 * base,u32 * size,u8 * target,u8 * attr,u64 * remap)107 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
108 				   int win, int *enabled, u64 *base,
109 				   u32 *size, u8 *target, u8 *attr,
110 				   u64 *remap)
111 {
112 	void __iomem *addr = mbus->mbuswins_base +
113 		mbus->soc->win_cfg_offset(win);
114 	u32 basereg = readl(addr + WIN_BASE_OFF);
115 	u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
116 
117 	if (!(ctrlreg & WIN_CTRL_ENABLE)) {
118 		*enabled = 0;
119 		return;
120 	}
121 
122 	*enabled = 1;
123 	*base = ((u64)basereg & WIN_BASE_HIGH) << 32;
124 	*base |= (basereg & WIN_BASE_LOW);
125 	*size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
126 
127 	if (target)
128 		*target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
129 
130 	if (attr)
131 		*attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
132 
133 	if (remap) {
134 		if (win < mbus->soc->num_remappable_wins) {
135 			u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
136 			u32 remap_hi  = readl(addr + WIN_REMAP_HI_OFF);
137 			*remap = ((u64)remap_hi << 32) | remap_low;
138 		} else {
139 			*remap = 0;
140 		}
141 	}
142 }
143 
mvebu_mbus_disable_window(struct mvebu_mbus_state * mbus,int win)144 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
145 				      int win)
146 {
147 	void __iomem *addr;
148 
149 	addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
150 
151 	writel(0, addr + WIN_BASE_OFF);
152 	writel(0, addr + WIN_CTRL_OFF);
153 	if (win < mbus->soc->num_remappable_wins) {
154 		writel(0, addr + WIN_REMAP_LO_OFF);
155 		writel(0, addr + WIN_REMAP_HI_OFF);
156 	}
157 }
158 
159 /* Checks whether the given window number is available */
mvebu_mbus_window_is_free(struct mvebu_mbus_state * mbus,const int win)160 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
161 				     const int win)
162 {
163 	void __iomem *addr = mbus->mbuswins_base +
164 		mbus->soc->win_cfg_offset(win);
165 	u32 ctrl = readl(addr + WIN_CTRL_OFF);
166 	return !(ctrl & WIN_CTRL_ENABLE);
167 }
168 
169 /*
170  * Checks whether the given (base, base+size) area doesn't overlap an
171  * existing region
172  */
mvebu_mbus_window_conflicts(struct mvebu_mbus_state * mbus,phys_addr_t base,size_t size,u8 target,u8 attr)173 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
174 				       phys_addr_t base, size_t size,
175 				       u8 target, u8 attr)
176 {
177 	u64 end = (u64)base + size;
178 	int win;
179 
180 	for (win = 0; win < mbus->soc->num_wins; win++) {
181 		u64 wbase, wend;
182 		u32 wsize;
183 		u8 wtarget, wattr;
184 		int enabled;
185 
186 		mvebu_mbus_read_window(mbus, win,
187 				       &enabled, &wbase, &wsize,
188 				       &wtarget, &wattr, NULL);
189 
190 		if (!enabled)
191 			continue;
192 
193 		wend = wbase + wsize;
194 
195 		/*
196 		 * Check if the current window overlaps with the
197 		 * proposed physical range
198 		 */
199 		if ((u64)base < wend && end > wbase)
200 			return 0;
201 
202 		/*
203 		 * Check if target/attribute conflicts
204 		 */
205 		if (target == wtarget && attr == wattr)
206 			return 0;
207 	}
208 
209 	return 1;
210 }
211 
mvebu_mbus_find_window(struct mvebu_mbus_state * mbus,phys_addr_t base,size_t size)212 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
213 				  phys_addr_t base, size_t size)
214 {
215 	int win;
216 
217 	for (win = 0; win < mbus->soc->num_wins; win++) {
218 		u64 wbase;
219 		u32 wsize;
220 		int enabled;
221 
222 		mvebu_mbus_read_window(mbus, win,
223 				       &enabled, &wbase, &wsize,
224 				       NULL, NULL, NULL);
225 
226 		if (!enabled)
227 			continue;
228 
229 		if (base == wbase && size == wsize)
230 			return win;
231 	}
232 
233 	return -ENODEV;
234 }
235 
mvebu_mbus_setup_window(struct mvebu_mbus_state * mbus,int win,phys_addr_t base,size_t size,phys_addr_t remap,u8 target,u8 attr)236 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
237 				   int win, phys_addr_t base, size_t size,
238 				   phys_addr_t remap, u8 target,
239 				   u8 attr)
240 {
241 	void __iomem *addr = mbus->mbuswins_base +
242 		mbus->soc->win_cfg_offset(win);
243 	u32 ctrl, remap_addr;
244 
245 	ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
246 		(attr << WIN_CTRL_ATTR_SHIFT)    |
247 		(target << WIN_CTRL_TGT_SHIFT)   |
248 		WIN_CTRL_ENABLE;
249 
250 	writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
251 	writel(ctrl, addr + WIN_CTRL_OFF);
252 	if (win < mbus->soc->num_remappable_wins) {
253 		if (remap == MVEBU_MBUS_NO_REMAP)
254 			remap_addr = base;
255 		else
256 			remap_addr = remap;
257 		writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
258 		writel(0, addr + WIN_REMAP_HI_OFF);
259 	}
260 
261 	return 0;
262 }
263 
mvebu_mbus_alloc_window(struct mvebu_mbus_state * mbus,phys_addr_t base,size_t size,phys_addr_t remap,u8 target,u8 attr)264 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
265 				   phys_addr_t base, size_t size,
266 				   phys_addr_t remap, u8 target,
267 				   u8 attr)
268 {
269 	int win;
270 
271 	if (remap == MVEBU_MBUS_NO_REMAP) {
272 		for (win = mbus->soc->num_remappable_wins;
273 		     win < mbus->soc->num_wins; win++)
274 			if (mvebu_mbus_window_is_free(mbus, win))
275 				return mvebu_mbus_setup_window(mbus, win, base,
276 							       size, remap,
277 							       target, attr);
278 	}
279 
280 
281 	for (win = 0; win < mbus->soc->num_wins; win++)
282 		if (mvebu_mbus_window_is_free(mbus, win))
283 			return mvebu_mbus_setup_window(mbus, win, base, size,
284 						       remap, target, attr);
285 
286 	return -ENOMEM;
287 }
288 
289 /*
290  * SoC-specific functions and definitions
291  */
292 
armada_370_xp_mbus_win_offset(int win)293 static unsigned int armada_370_xp_mbus_win_offset(int win)
294 {
295 	/* The register layout is a bit annoying and the below code
296 	 * tries to cope with it.
297 	 * - At offset 0x0, there are the registers for the first 8
298 	 *   windows, with 4 registers of 32 bits per window (ctrl,
299 	 *   base, remap low, remap high)
300 	 * - Then at offset 0x80, there is a hole of 0x10 bytes for
301 	 *   the internal registers base address and internal units
302 	 *   sync barrier register.
303 	 * - Then at offset 0x90, there the registers for 12
304 	 *   windows, with only 2 registers of 32 bits per window
305 	 *   (ctrl, base).
306 	 */
307 	if (win < 8)
308 		return win << 4;
309 	else
310 		return 0x90 + ((win - 8) << 3);
311 }
312 
orion5x_mbus_win_offset(int win)313 static unsigned int orion5x_mbus_win_offset(int win)
314 {
315 	return win << 4;
316 }
317 
mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state * mbus)318 static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
319 {
320 	int i;
321 	int cs;
322 
323 	mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
324 
325 	for (i = 0, cs = 0; i < 4; i++) {
326 		u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
327 		u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
328 
329 		/*
330 		 * We only take care of entries for which the chip
331 		 * select is enabled, and that don't have high base
332 		 * address bits set (devices can only access the first
333 		 * 32 bits of the memory).
334 		 */
335 		if ((size & DDR_SIZE_ENABLED) &&
336 		    !(base & DDR_BASE_CS_HIGH_MASK)) {
337 			struct mbus_dram_window *w;
338 
339 			w = &mbus_dram_info.cs[cs++];
340 			w->cs_index = i;
341 			w->mbus_attr = 0xf & ~(1 << i);
342 			w->base = base & DDR_BASE_CS_LOW_MASK;
343 			w->size = (size | ~DDR_SIZE_MASK) + 1;
344 		}
345 	}
346 	mbus_dram_info.num_cs = cs;
347 }
348 
349 static const struct mvebu_mbus_soc_data
350 armada_370_xp_mbus_data __maybe_unused = {
351 	.num_wins            = 20,
352 	.num_remappable_wins = 8,
353 	.win_cfg_offset      = armada_370_xp_mbus_win_offset,
354 	.setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
355 };
356 
357 static const struct mvebu_mbus_soc_data
358 kirkwood_mbus_data __maybe_unused = {
359 	.num_wins            = 8,
360 	.num_remappable_wins = 4,
361 	.win_cfg_offset      = orion5x_mbus_win_offset,
362 	.setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
363 };
364 
365 /*
366  * Public API of the driver
367  */
mvebu_mbus_dram_info(void)368 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
369 {
370 	return &mbus_dram_info;
371 }
372 
mvebu_mbus_add_window_remap_by_id(unsigned int target,unsigned int attribute,phys_addr_t base,size_t size,phys_addr_t remap)373 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
374 				      unsigned int attribute,
375 				      phys_addr_t base, size_t size,
376 				      phys_addr_t remap)
377 {
378 	struct mvebu_mbus_state *s = &mbus_state;
379 
380 	if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
381 		printf("Cannot add window '%x:%x', conflicts with another window\n",
382 		       target, attribute);
383 		return -EINVAL;
384 	}
385 
386 	return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
387 }
388 
mvebu_mbus_add_window_by_id(unsigned int target,unsigned int attribute,phys_addr_t base,size_t size)389 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
390 				phys_addr_t base, size_t size)
391 {
392 	return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
393 						 size, MVEBU_MBUS_NO_REMAP);
394 }
395 
mvebu_mbus_del_window(phys_addr_t base,size_t size)396 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
397 {
398 	int win;
399 
400 	win = mvebu_mbus_find_window(&mbus_state, base, size);
401 	if (win < 0)
402 		return win;
403 
404 	mvebu_mbus_disable_window(&mbus_state, win);
405 	return 0;
406 }
407 
mvebu_mbus_get_lowest_base(struct mvebu_mbus_state * mbus,phys_addr_t * base)408 static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
409 				       phys_addr_t *base)
410 {
411 	int win;
412 	*base = 0xffffffff;
413 
414 	for (win = 0; win < mbus->soc->num_wins; win++) {
415 		u64 wbase;
416 		u32 wsize;
417 		u8 wtarget, wattr;
418 		int enabled;
419 
420 		mvebu_mbus_read_window(mbus, win,
421 				       &enabled, &wbase, &wsize,
422 				       &wtarget, &wattr, NULL);
423 
424 		if (!enabled)
425 			continue;
426 
427 		if (wbase < *base)
428 			*base = wbase;
429 	}
430 }
431 
mvebu_config_mbus_bridge(struct mvebu_mbus_state * mbus)432 static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
433 {
434 	phys_addr_t base;
435 	u32 val;
436 	u32 size;
437 
438 	/* Set MBUS bridge base/ctrl */
439 	mvebu_mbus_get_lowest_base(&mbus_state, &base);
440 
441 	size = 0xffffffff - base + 1;
442 	if (!is_power_of_2(size)) {
443 		/* Round up to next power of 2 */
444 		size = 1 << (ffs(base) + 1);
445 		base = 0xffffffff - size + 1;
446 	}
447 
448 	/* Now write base and size */
449 	writel(base, MBUS_BRIDGE_WIN_BASE_REG);
450 	/* Align window size to 64KiB */
451 	val = (size / (64 << 10)) - 1;
452 	writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
453 }
454 
mbus_dt_setup_win(struct mvebu_mbus_state * mbus,u32 base,u32 size,u8 target,u8 attr)455 int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
456 		      u32 base, u32 size, u8 target, u8 attr)
457 {
458 	if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
459 		printf("Cannot add window '%04x:%04x', conflicts with another window\n",
460 		       target, attr);
461 		return -EBUSY;
462 	}
463 
464 	/*
465 	 * In U-Boot we first try to add the mbus window to the remap windows.
466 	 * If this fails, lets try to add the windows to the non-remap windows.
467 	 */
468 	if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
469 		if (mvebu_mbus_alloc_window(mbus, base, size,
470 					    MVEBU_MBUS_NO_REMAP, target, attr))
471 			return -ENOMEM;
472 	}
473 
474 	/*
475 	 * Re-configure the mbus bridge registers each time this function
476 	 * is called. Since it may get called from the board code in
477 	 * later boot stages as well.
478 	 */
479 	mvebu_config_mbus_bridge(mbus);
480 
481 	return 0;
482 }
483 
mvebu_mbus_probe(struct mbus_win windows[],int count)484 int mvebu_mbus_probe(struct mbus_win windows[], int count)
485 {
486 	int win;
487 	int ret;
488 	int i;
489 
490 #if defined(CONFIG_KIRKWOOD)
491 	mbus_state.soc = &kirkwood_mbus_data;
492 #endif
493 #if defined(CONFIG_ARCH_MVEBU)
494 	mbus_state.soc = &armada_370_xp_mbus_data;
495 #endif
496 
497 	mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
498 	mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
499 
500 	for (win = 0; win < mbus_state.soc->num_wins; win++)
501 		mvebu_mbus_disable_window(&mbus_state, win);
502 
503 	mbus_state.soc->setup_cpu_target(&mbus_state);
504 
505 	/* Setup statically declared windows in the DT */
506 	for (i = 0; i < count; i++) {
507 		u32 base, size;
508 		u8 target, attr;
509 
510 		target = windows[i].target;
511 		attr = windows[i].attr;
512 		base = windows[i].base;
513 		size = windows[i].size;
514 		ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
515 		if (ret < 0)
516 			return ret;
517 	}
518 
519 	return 0;
520 }
521