Searched refs:DPLL (Results 1 – 5 of 5) sorted by relevance
| /external/u-boot/arch/arm/mach-exynos/include/mach/ |
| D | clk.h | 19 #define DPLL 9 macro
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | cru_rk3368.h | 16 DPLL, enumerator
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| /external/u-boot/board/rockchip/evb_rv1108/ |
| D | README | 37 APLL: 600000000 DPLL:792000000 GPLL:384000000
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| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rk3368.c | 147 dpll = rkclk_pll_get_rate(cru, DPLL); in rkclk_init()
305 rkclk_set_pll(cru, DPLL, dpll_cfg); in rk3368_ddr_set_clk()
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| /external/u-boot/arch/arm/mach-exynos/ |
| D | clock.c | 1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
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