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Searched refs:DQ_NUM (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_pbs.c42 static u32 skew_array[(MAX_PUP_NUM) * DQ_NUM] = { 0 };
45 extern u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM];
47 extern u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM];
57 extern u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM];
83 u32 skew_sum_array[MAX_PUP_NUM][DQ_NUM] = { {0} }; in ddr3_pbs_tx()
89 u32 pattern_skew_array[MAX_PUP_NUM][DQ_NUM] = { {0} }; in ddr3_pbs_tx()
125 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
173 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
200 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
253 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
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Dddr3_dqs.c80 extern u32 killer_pattern_32b[DQ_NUM][LEN_SPECIAL_PATTERN];
81 extern u32 killer_pattern_64b[DQ_NUM][LEN_SPECIAL_PATTERN];
82 extern int per_bit_data[MAX_PUP_NUM][DQ_NUM];
84 extern u32 killer_pattern[DQ_NUM][LEN_16BIT_KILLER_PATTERN];
85 extern u32 killer_pattern_32b[DQ_NUM][LEN_SPECIAL_PATTERN];
87 extern int per_bit_data[MAX_PUP_NUM][DQ_NUM];
90 extern u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN];
314 u8 analog_pbs[DQ_NUM][MAX_PUP_NUM][DQ_NUM][2]; in ddr3_find_adll_limits()
315 u8 analog_pbs_sum[MAX_PUP_NUM][DQ_NUM][2]; in ddr3_find_adll_limits()
346 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
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Dddr3_patterns_64bit.h61 u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
336 u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
611 u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
911 u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {
Dddr3_sdram.c24 extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
28 u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
30 u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
32 int per_bit_data[MAX_PUP_NUM][DQ_NUM];
114 for (dq = 0; dq < DQ_NUM; dq++) { in compare_pattern_v1()
287 u32 pbs_write_pup[DQ_NUM] = { 0 }; in ddr3_sdram_pbs_compare()
363 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_sdram_pbs_compare()
392 skew_array[tmp_pup * DQ_NUM + dq] = in ddr3_sdram_pbs_compare()
404 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_sdram_pbs_compare()
Dddr3_hw_training.h136 #define DQ_NUM 8 macro
Dddr3_hw_training.c738 for (dq = 0; dq <= DQ_NUM; in ddr3_save_training()
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_patterns_64bit.h62 u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
337 u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
612 u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
912 u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {