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Searched refs:DR4 (Results 1 – 25 of 32) sorted by relevance

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/external/libdrm/intel/
Dintel_bufmgr.c152 drm_clip_rect_t * cliprects, int num_cliprects, int DR4) in drm_intel_bo_exec() argument
154 return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4); in drm_intel_bo_exec()
159 drm_clip_rect_t *cliprects, int num_cliprects, int DR4, in drm_intel_bo_mrb_exec() argument
164 cliprects, num_cliprects, DR4, in drm_intel_bo_mrb_exec()
171 cliprects, num_cliprects, DR4); in drm_intel_bo_mrb_exec()
Dintel_bufmgr_priv.h200 int DR4);
207 int DR4, unsigned flags);
Dintel_bufmgr.h145 struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
147 struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
Dintel_bufmgr_gem.c2290 drm_clip_rect_t * cliprects, int num_cliprects, int DR4) in drm_intel_gem_bo_exec() argument
2316 execbuf.DR4 = DR4; in drm_intel_gem_bo_exec()
2357 drm_clip_rect_t *cliprects, int num_cliprects, int DR4, in do_exec2() argument
2406 execbuf.DR4 = DR4; in do_exec2()
2467 int DR4) in drm_intel_gem_bo_exec2() argument
2469 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, in drm_intel_gem_bo_exec2()
2475 drm_clip_rect_t *cliprects, int num_cliprects, int DR4, in drm_intel_gem_bo_mrb_exec2() argument
2478 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, in drm_intel_gem_bo_mrb_exec2()
Dintel_bufmgr_fake.c1427 drm_clip_rect_t * cliprects, int num_cliprects, int DR4) in drm_intel_fake_bo_exec() argument
1471 batch.DR4 = DR4; in drm_intel_fake_bo_exec()
/external/mesa3d/include/drm-uapi/
Di915_drm.h346 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ member
358 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ member
792 __u32 DR4; member
895 __u32 DR4; member
/external/libdrm/include/drm/
Di915_drm.h388 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ member
400 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ member
834 __u32 DR4; member
937 __u32 DR4; member
/external/kernel-headers/original/uapi/drm/
Di915_drm.h388 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ member
400 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ member
864 __u32 DR4; member
967 __u32 DR4; member
/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmLexer.cpp112 case '4': RegNo = X86::DR4; break; in LexTokenATT()
DX86AsmParser.cpp468 case '4': RegNo = X86::DR4; break; in ParseRegister()
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 … CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8 DR9…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h255 ENTRY(DR4) \
/external/capstone/arch/X86/
DX86DisassemblerDecoder.h355 ENTRY(DR4) \
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h341 ENTRY(DR4) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h341 ENTRY(DR4) \
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp215 case X86::CR4: case X86::CR12: case X86::DR4: return 4; in getX86RegNum()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenRegisterInfo.inc56 DR4 = 37,
285 const unsigned DR4_Overlaps[] = { X86::DR4, 0 };
602 { "DR4", DR4_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
910 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7,
1469 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, false );
1630 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, false );
1791 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, false );
1957 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, true );
2118 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, true );
2279 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, true );
[all …]
DX86RegisterInfo.td242 def DR4 : Register<"dr4">;
/external/mesa3d/src/intel/vulkan/
Danv_queue.c95 execbuf.DR4 = 0; in anv_device_submit_simple_batch()
Danv_batch_chain.c1377 .DR4 = 0, in setup_execbuf_for_cmd_buffer()
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td270 def DR4 : X86Reg<"dr4", 4>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td319 def DR4 : X86Reg<"dr4", 4>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h133 #define DR4 dr4 macro
195 #define DR4 %db4 macro
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp967 case '4': RegNo = X86::DR4; break; in ParseRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp1156 case '4': RegNo = X86::DR4; break; in ParseRegister()

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