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Searched refs:DRM_ERROR (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_validate.c63 DRM_ERROR("unknown cpp: %d\n", cpp); in utile_width()
80 DRM_ERROR("unknown cpp: %d\n", cpp); in utile_height()
103 DRM_ERROR("BO index %d greater than BO count %d\n", in vc4_use_bo()
111 DRM_ERROR("Trying to use shader BO as something other than " in vc4_use_bo()
166 DRM_ERROR("Surface dimesions (%d,%d) too large", width, height); in vc4_check_tex_size()
184 DRM_ERROR("buffer tiling %d unsupported\n", tiling_format); in vc4_check_tex_size()
193 DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n", in vc4_check_tex_size()
207 DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n"); in validate_flush()
219 DRM_ERROR("Duplicate VC4_PACKET_START_TILE_BINNING\n"); in validate_start_tile_binning()
225 DRM_ERROR("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n"); in validate_start_tile_binning()
[all …]
Dvc4_validate_shaders.c199 DRM_ERROR("direct TMU read used small immediate\n"); in check_tmu_write()
208 DRM_ERROR("direct TMU load wasn't an add\n"); in check_tmu_write()
219 DRM_ERROR("direct TMU load wasn't clamped\n"); in check_tmu_write()
225 DRM_ERROR("direct TMU load wasn't clamped\n"); in check_tmu_write()
237 DRM_ERROR("direct TMU load didn't add to a uniform\n"); in check_tmu_write()
245 DRM_ERROR("uniform read in the same instruction as " in check_tmu_write()
252 DRM_ERROR("TMU%d got too many parameters before dispatch\n", in check_tmu_write()
264 DRM_ERROR("Texturing with undefined uniform address\n"); in check_tmu_write()
329 DRM_ERROR("uniforms address change must be " in validate_uniform_address_write()
335 DRM_ERROR("Uniform address reset must be an ADD.\n"); in validate_uniform_address_write()
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Dvc4_render_cl.c387 DRM_ERROR("surface offset %d > BO size %zd\n", in vc4_full_res_bounds_check()
394 DRM_ERROR("MSAA tile %d, %d out of bounds " in vc4_full_res_bounds_check()
410 DRM_ERROR("MSAA surface had nonzero flags/bits\n"); in vc4_rcl_msaa_surface_setup()
422 DRM_ERROR("MSAA write must be 16b aligned.\n"); in vc4_rcl_msaa_surface_setup()
443 DRM_ERROR("Extra flags set\n"); in vc4_rcl_surface_setup()
456 DRM_ERROR("general zs write may not be a full-res.\n"); in vc4_rcl_surface_setup()
461 DRM_ERROR("load/store general bits set with " in vc4_rcl_surface_setup()
476 DRM_ERROR("Unknown bits in load/store: 0x%04x\n", in vc4_rcl_surface_setup()
482 DRM_ERROR("Bad tiling format\n"); in vc4_rcl_surface_setup()
488 DRM_ERROR("No color format should be set for ZS\n"); in vc4_rcl_surface_setup()
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Dvc4_gem.c52 DRM_ERROR("overflow in exec arguments\n"); in vc4_get_bcl()
65 DRM_ERROR("Failed to allocate storage for copying " in vc4_get_bcl()
80 DRM_ERROR("Failed to copy in bin cl\n"); in vc4_get_bcl()
88 DRM_ERROR("Failed to copy in shader recs\n"); in vc4_get_bcl()
96 DRM_ERROR("Failed to copy in uniforms cl\n"); in vc4_get_bcl()
103 DRM_ERROR("Couldn't allocate BO for exec\n"); in vc4_get_bcl()
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_simulator_validate.h40 #define DRM_ERROR(...) fprintf(stderr, __VA_ARGS__) macro