1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <common.h>
4 #include <malloc.h>
5 #include <net.h>
6 #include <netdev.h>
7 #include <pci.h>
8
9 #undef DEBUG_SROM
10 #undef DEBUG_SROM2
11
12 #undef UPDATE_SROM
13
14 /* PCI Registers.
15 */
16 #define PCI_CFDA_PSM 0x43
17
18 #define CFRV_RN 0x000000f0 /* Revision Number */
19
20 #define WAKEUP 0x00 /* Power Saving Wakeup */
21 #define SLEEP 0x80 /* Power Saving Sleep Mode */
22
23 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
24
25 /* Ethernet chip registers.
26 */
27 #define DE4X5_BMR 0x000 /* Bus Mode Register */
28 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
29 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
30 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
31 #define DE4X5_STS 0x028 /* Status Register */
32 #define DE4X5_OMR 0x030 /* Operation Mode Register */
33 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
34 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
35
36 /* Register bits.
37 */
38 #define BMR_SWR 0x00000001 /* Software Reset */
39 #define STS_TS 0x00700000 /* Transmit Process State */
40 #define STS_RS 0x000e0000 /* Receive Process State */
41 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
42 #define OMR_SR 0x00000002 /* Start/Stop Receive */
43 #define OMR_PS 0x00040000 /* Port Select */
44 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
45 #define OMR_PM 0x00000080 /* Pass All Multicast */
46
47 /* Descriptor bits.
48 */
49 #define R_OWN 0x80000000 /* Own Bit */
50 #define RD_RER 0x02000000 /* Receive End Of Ring */
51 #define RD_LS 0x00000100 /* Last Descriptor */
52 #define RD_ES 0x00008000 /* Error Summary */
53 #define TD_TER 0x02000000 /* Transmit End Of Ring */
54 #define T_OWN 0x80000000 /* Own Bit */
55 #define TD_LS 0x40000000 /* Last Segment */
56 #define TD_FS 0x20000000 /* First Segment */
57 #define TD_ES 0x00008000 /* Error Summary */
58 #define TD_SET 0x08000000 /* Setup Packet */
59
60 /* The EEPROM commands include the alway-set leading bit. */
61 #define SROM_WRITE_CMD 5
62 #define SROM_READ_CMD 6
63 #define SROM_ERASE_CMD 7
64
65 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
66 #define SROM_RD 0x00004000 /* Read from Boot ROM */
67 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
68 #define EE_WRITE_0 0x4801
69 #define EE_WRITE_1 0x4805
70 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
71 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
72
73 #define DT_IN 0x00000004 /* Serial Data In */
74 #define DT_CLK 0x00000002 /* Serial ROM Clock */
75 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
76
77 #define POLL_DEMAND 1
78
79 #ifdef CONFIG_TULIP_FIX_DAVICOM
80 #define RESET_DM9102(dev) {\
81 unsigned long i;\
82 i=INL(dev, 0x0);\
83 udelay(1000);\
84 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
85 udelay(1000);\
86 }
87 #else
88 #define RESET_DE4X5(dev) {\
89 int i;\
90 i=INL(dev, DE4X5_BMR);\
91 udelay(1000);\
92 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
93 udelay(1000);\
94 OUTL(dev, i, DE4X5_BMR);\
95 udelay(1000);\
96 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
97 udelay(1000);\
98 }
99 #endif
100
101 #define START_DE4X5(dev) {\
102 s32 omr; \
103 omr = INL(dev, DE4X5_OMR);\
104 omr |= OMR_ST | OMR_SR;\
105 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
106 }
107
108 #define STOP_DE4X5(dev) {\
109 s32 omr; \
110 omr = INL(dev, DE4X5_OMR);\
111 omr &= ~(OMR_ST|OMR_SR);\
112 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
113 }
114
115 #define NUM_RX_DESC PKTBUFSRX
116 #ifndef CONFIG_TULIP_FIX_DAVICOM
117 #define NUM_TX_DESC 1 /* Number of TX descriptors */
118 #else
119 #define NUM_TX_DESC 4
120 #endif
121 #define RX_BUFF_SZ PKTSIZE_ALIGN
122
123 #define TOUT_LOOP 1000000
124
125 #define SETUP_FRAME_LEN 192
126 #define ETH_ALEN 6
127
128 struct de4x5_desc {
129 volatile s32 status;
130 u32 des1;
131 u32 buf;
132 u32 next;
133 };
134
135 static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
136 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
137 static int rx_new; /* RX descriptor ring pointer */
138 static int tx_new; /* TX descriptor ring pointer */
139
140 static char rxRingSize;
141 static char txRingSize;
142
143 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
144 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
145 static int getfrom_srom(struct eth_device* dev, u_long addr);
146 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
147 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
148 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
149 #ifdef UPDATE_SROM
150 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
151 static void update_srom(struct eth_device *dev, bd_t *bis);
152 #endif
153 #ifndef CONFIG_TULIP_FIX_DAVICOM
154 static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
155 static void read_hw_addr(struct eth_device* dev, bd_t * bis);
156 #endif /* CONFIG_TULIP_FIX_DAVICOM */
157 static void send_setup_frame(struct eth_device* dev, bd_t * bis);
158
159 static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
160 static int dc21x4x_send(struct eth_device *dev, void *packet, int length);
161 static int dc21x4x_recv(struct eth_device* dev);
162 static void dc21x4x_halt(struct eth_device* dev);
163 #ifdef CONFIG_TULIP_SELECT_MEDIA
164 extern void dc21x4x_select_media(struct eth_device* dev);
165 #endif
166
167 #if defined(CONFIG_E500)
168 #define phys_to_bus(a) (a)
169 #else
170 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
171 #endif
172
INL(struct eth_device * dev,u_long addr)173 static int INL(struct eth_device* dev, u_long addr)
174 {
175 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
176 }
177
OUTL(struct eth_device * dev,int command,u_long addr)178 static void OUTL(struct eth_device* dev, int command, u_long addr)
179 {
180 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
181 }
182
183 static struct pci_device_id supported[] = {
184 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
185 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
186 #ifdef CONFIG_TULIP_FIX_DAVICOM
187 { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
188 #endif
189 { }
190 };
191
dc21x4x_initialize(bd_t * bis)192 int dc21x4x_initialize(bd_t *bis)
193 {
194 int idx=0;
195 int card_number = 0;
196 unsigned int cfrv;
197 unsigned char timer;
198 pci_dev_t devbusfn;
199 unsigned int iobase;
200 unsigned short status;
201 struct eth_device* dev;
202
203 while(1) {
204 devbusfn = pci_find_devices(supported, idx++);
205 if (devbusfn == -1) {
206 break;
207 }
208
209 /* Get the chip configuration revision register. */
210 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
211
212 #ifndef CONFIG_TULIP_FIX_DAVICOM
213 if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
214 printf("Error: The chip is not DC21143.\n");
215 continue;
216 }
217 #endif
218
219 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
220 status |=
221 #ifdef CONFIG_TULIP_USE_IO
222 PCI_COMMAND_IO |
223 #else
224 PCI_COMMAND_MEMORY |
225 #endif
226 PCI_COMMAND_MASTER;
227 pci_write_config_word(devbusfn, PCI_COMMAND, status);
228
229 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
230 #ifdef CONFIG_TULIP_USE_IO
231 if (!(status & PCI_COMMAND_IO)) {
232 printf("Error: Can not enable I/O access.\n");
233 continue;
234 }
235 #else
236 if (!(status & PCI_COMMAND_MEMORY)) {
237 printf("Error: Can not enable MEMORY access.\n");
238 continue;
239 }
240 #endif
241
242 if (!(status & PCI_COMMAND_MASTER)) {
243 printf("Error: Can not enable Bus Mastering.\n");
244 continue;
245 }
246
247 /* Check the latency timer for values >= 0x60. */
248 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
249
250 if (timer < 0x60) {
251 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
252 }
253
254 #ifdef CONFIG_TULIP_USE_IO
255 /* read BAR for memory space access */
256 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
257 iobase &= PCI_BASE_ADDRESS_IO_MASK;
258 #else
259 /* read BAR for memory space access */
260 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
261 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
262 #endif
263 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
264
265 dev = (struct eth_device*) malloc(sizeof *dev);
266
267 if (!dev) {
268 printf("Can not allocalte memory of dc21x4x\n");
269 break;
270 }
271 memset(dev, 0, sizeof(*dev));
272
273 #ifdef CONFIG_TULIP_FIX_DAVICOM
274 sprintf(dev->name, "Davicom#%d", card_number);
275 #else
276 sprintf(dev->name, "dc21x4x#%d", card_number);
277 #endif
278
279 #ifdef CONFIG_TULIP_USE_IO
280 dev->iobase = pci_io_to_phys(devbusfn, iobase);
281 #else
282 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
283 #endif
284 dev->priv = (void*) devbusfn;
285 dev->init = dc21x4x_init;
286 dev->halt = dc21x4x_halt;
287 dev->send = dc21x4x_send;
288 dev->recv = dc21x4x_recv;
289
290 /* Ensure we're not sleeping. */
291 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
292
293 udelay(10 * 1000);
294
295 #ifndef CONFIG_TULIP_FIX_DAVICOM
296 read_hw_addr(dev, bis);
297 #endif
298 eth_register(dev);
299
300 card_number++;
301 }
302
303 return card_number;
304 }
305
dc21x4x_init(struct eth_device * dev,bd_t * bis)306 static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
307 {
308 int i;
309 int devbusfn = (int) dev->priv;
310
311 /* Ensure we're not sleeping. */
312 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
313
314 #ifdef CONFIG_TULIP_FIX_DAVICOM
315 RESET_DM9102(dev);
316 #else
317 RESET_DE4X5(dev);
318 #endif
319
320 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
321 printf("Error: Cannot reset ethernet controller.\n");
322 return -1;
323 }
324
325 #ifdef CONFIG_TULIP_SELECT_MEDIA
326 dc21x4x_select_media(dev);
327 #else
328 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
329 #endif
330
331 for (i = 0; i < NUM_RX_DESC; i++) {
332 rx_ring[i].status = cpu_to_le32(R_OWN);
333 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
334 rx_ring[i].buf = cpu_to_le32(
335 phys_to_bus((u32)net_rx_packets[i]));
336 #ifdef CONFIG_TULIP_FIX_DAVICOM
337 rx_ring[i].next = cpu_to_le32(
338 phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC]));
339 #else
340 rx_ring[i].next = 0;
341 #endif
342 }
343
344 for (i=0; i < NUM_TX_DESC; i++) {
345 tx_ring[i].status = 0;
346 tx_ring[i].des1 = 0;
347 tx_ring[i].buf = 0;
348
349 #ifdef CONFIG_TULIP_FIX_DAVICOM
350 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
351 #else
352 tx_ring[i].next = 0;
353 #endif
354 }
355
356 rxRingSize = NUM_RX_DESC;
357 txRingSize = NUM_TX_DESC;
358
359 /* Write the end of list marker to the descriptor lists. */
360 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
361 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
362
363 /* Tell the adapter where the TX/RX rings are located. */
364 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
365 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
366
367 START_DE4X5(dev);
368
369 tx_new = 0;
370 rx_new = 0;
371
372 send_setup_frame(dev, bis);
373
374 return 0;
375 }
376
dc21x4x_send(struct eth_device * dev,void * packet,int length)377 static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
378 {
379 int status = -1;
380 int i;
381
382 if (length <= 0) {
383 printf("%s: bad packet size: %d\n", dev->name, length);
384 goto Done;
385 }
386
387 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
388 if (i >= TOUT_LOOP) {
389 printf("%s: tx error buffer not ready\n", dev->name);
390 goto Done;
391 }
392 }
393
394 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
395 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
396 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
397
398 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
399
400 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
401 if (i >= TOUT_LOOP) {
402 printf(".%s: tx buffer not ready\n", dev->name);
403 goto Done;
404 }
405 }
406
407 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
408 #if 0 /* test-only */
409 printf("TX error status = 0x%08X\n",
410 le32_to_cpu(tx_ring[tx_new].status));
411 #endif
412 tx_ring[tx_new].status = 0x0;
413 goto Done;
414 }
415
416 status = length;
417
418 Done:
419 tx_new = (tx_new+1) % NUM_TX_DESC;
420 return status;
421 }
422
dc21x4x_recv(struct eth_device * dev)423 static int dc21x4x_recv(struct eth_device* dev)
424 {
425 s32 status;
426 int length = 0;
427
428 for ( ; ; ) {
429 status = (s32)le32_to_cpu(rx_ring[rx_new].status);
430
431 if (status & R_OWN) {
432 break;
433 }
434
435 if (status & RD_LS) {
436 /* Valid frame status.
437 */
438 if (status & RD_ES) {
439
440 /* There was an error.
441 */
442 printf("RX error status = 0x%08X\n", status);
443 } else {
444 /* A valid frame received.
445 */
446 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
447
448 /* Pass the packet up to the protocol
449 * layers.
450 */
451 net_process_received_packet(
452 net_rx_packets[rx_new], length - 4);
453 }
454
455 /* Change buffer ownership for this frame, back
456 * to the adapter.
457 */
458 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
459 }
460
461 /* Update entry information.
462 */
463 rx_new = (rx_new + 1) % rxRingSize;
464 }
465
466 return length;
467 }
468
dc21x4x_halt(struct eth_device * dev)469 static void dc21x4x_halt(struct eth_device* dev)
470 {
471 int devbusfn = (int) dev->priv;
472
473 STOP_DE4X5(dev);
474 OUTL(dev, 0, DE4X5_SICR);
475
476 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
477 }
478
send_setup_frame(struct eth_device * dev,bd_t * bis)479 static void send_setup_frame(struct eth_device* dev, bd_t *bis)
480 {
481 int i;
482 char setup_frame[SETUP_FRAME_LEN];
483 char *pa = &setup_frame[0];
484
485 memset(pa, 0xff, SETUP_FRAME_LEN);
486
487 for (i = 0; i < ETH_ALEN; i++) {
488 *(pa + (i & 1)) = dev->enetaddr[i];
489 if (i & 0x01) {
490 pa += 4;
491 }
492 }
493
494 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
495 if (i >= TOUT_LOOP) {
496 printf("%s: tx error buffer not ready\n", dev->name);
497 goto Done;
498 }
499 }
500
501 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
502 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
503 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
504
505 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
506
507 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
508 if (i >= TOUT_LOOP) {
509 printf("%s: tx buffer not ready\n", dev->name);
510 goto Done;
511 }
512 }
513
514 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
515 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
516 }
517 tx_new = (tx_new+1) % NUM_TX_DESC;
518
519 Done:
520 return;
521 }
522
523 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
524 /* SROM Read and write routines.
525 */
526 static void
sendto_srom(struct eth_device * dev,u_int command,u_long addr)527 sendto_srom(struct eth_device* dev, u_int command, u_long addr)
528 {
529 OUTL(dev, command, addr);
530 udelay(1);
531 }
532
533 static int
getfrom_srom(struct eth_device * dev,u_long addr)534 getfrom_srom(struct eth_device* dev, u_long addr)
535 {
536 s32 tmp;
537
538 tmp = INL(dev, addr);
539 udelay(1);
540
541 return tmp;
542 }
543
544 /* Note: this routine returns extra data bits for size detection. */
do_read_eeprom(struct eth_device * dev,u_long ioaddr,int location,int addr_len)545 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
546 {
547 int i;
548 unsigned retval = 0;
549 int read_cmd = location | (SROM_READ_CMD << addr_len);
550
551 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
552 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
553
554 #ifdef DEBUG_SROM
555 printf(" EEPROM read at %d ", location);
556 #endif
557
558 /* Shift the read command bits out. */
559 for (i = 4 + addr_len; i >= 0; i--) {
560 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
561 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
562 udelay(10);
563 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
564 udelay(10);
565 #ifdef DEBUG_SROM2
566 printf("%X", getfrom_srom(dev, ioaddr) & 15);
567 #endif
568 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
569 }
570
571 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
572
573 #ifdef DEBUG_SROM2
574 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
575 #endif
576
577 for (i = 16; i > 0; i--) {
578 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
579 udelay(10);
580 #ifdef DEBUG_SROM2
581 printf("%X", getfrom_srom(dev, ioaddr) & 15);
582 #endif
583 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
584 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
585 udelay(10);
586 }
587
588 /* Terminate the EEPROM access. */
589 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
590
591 #ifdef DEBUG_SROM2
592 printf(" EEPROM value at %d is %5.5x.\n", location, retval);
593 #endif
594
595 return retval;
596 }
597 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
598
599 /* This executes a generic EEPROM command, typically a write or write
600 * enable. It returns the data output from the EEPROM, and thus may
601 * also be used for reads.
602 */
603 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
do_eeprom_cmd(struct eth_device * dev,u_long ioaddr,int cmd,int cmd_len)604 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
605 {
606 unsigned retval = 0;
607
608 #ifdef DEBUG_SROM
609 printf(" EEPROM op 0x%x: ", cmd);
610 #endif
611
612 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
613
614 /* Shift the command bits out. */
615 do {
616 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
617 sendto_srom(dev,dataval, ioaddr);
618 udelay(10);
619
620 #ifdef DEBUG_SROM2
621 printf("%X", getfrom_srom(dev,ioaddr) & 15);
622 #endif
623
624 sendto_srom(dev,dataval | DT_CLK, ioaddr);
625 udelay(10);
626 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
627 } while (--cmd_len >= 0);
628 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
629
630 /* Terminate the EEPROM access. */
631 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
632
633 #ifdef DEBUG_SROM
634 printf(" EEPROM result is 0x%5.5x.\n", retval);
635 #endif
636
637 return retval;
638 }
639 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
640
641 #ifndef CONFIG_TULIP_FIX_DAVICOM
read_srom(struct eth_device * dev,u_long ioaddr,int index)642 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
643 {
644 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
645
646 return do_eeprom_cmd(dev, ioaddr,
647 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
648 | 0xffff, 3 + ee_addr_size + 16);
649 }
650 #endif /* CONFIG_TULIP_FIX_DAVICOM */
651
652 #ifdef UPDATE_SROM
write_srom(struct eth_device * dev,u_long ioaddr,int index,int new_value)653 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
654 {
655 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
656 int i;
657 unsigned short newval;
658
659 udelay(10*1000); /* test-only */
660
661 #ifdef DEBUG_SROM
662 printf("ee_addr_size=%d.\n", ee_addr_size);
663 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
664 #endif
665
666 /* Enable programming modes. */
667 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
668
669 /* Do the actual write. */
670 do_eeprom_cmd(dev, ioaddr,
671 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
672 3 + ee_addr_size + 16);
673
674 /* Poll for write finished. */
675 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
676 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
677 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
678 break;
679
680 #ifdef DEBUG_SROM
681 printf(" Write finished after %d ticks.\n", i);
682 #endif
683
684 /* Disable programming. */
685 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
686
687 /* And read the result. */
688 newval = do_eeprom_cmd(dev, ioaddr,
689 (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
690 | 0xffff, 3 + ee_addr_size + 16);
691 #ifdef DEBUG_SROM
692 printf(" New value at offset %d is %4.4x.\n", index, newval);
693 #endif
694 return 1;
695 }
696 #endif
697
698 #ifndef CONFIG_TULIP_FIX_DAVICOM
read_hw_addr(struct eth_device * dev,bd_t * bis)699 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
700 {
701 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
702 int i, j = 0;
703
704 for (i = 0; i < (ETH_ALEN >> 1); i++) {
705 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
706 *p = le16_to_cpu(tmp);
707 j += *p++;
708 }
709
710 if ((j == 0) || (j == 0x2fffd)) {
711 memset (dev->enetaddr, 0, ETH_ALEN);
712 debug ("Warning: can't read HW address from SROM.\n");
713 goto Done;
714 }
715
716 return;
717
718 Done:
719 #ifdef UPDATE_SROM
720 update_srom(dev, bis);
721 #endif
722 return;
723 }
724 #endif /* CONFIG_TULIP_FIX_DAVICOM */
725
726 #ifdef UPDATE_SROM
update_srom(struct eth_device * dev,bd_t * bis)727 static void update_srom(struct eth_device *dev, bd_t *bis)
728 {
729 int i;
730 static unsigned short eeprom[0x40] = {
731 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
732 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
733 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
734 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
735 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
736 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
737 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
738 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
739 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
740 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
741 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
742 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
743 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
744 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
745 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
746 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
747 };
748 uchar enetaddr[6];
749
750 /* Ethernet Addr... */
751 if (!eth_env_get_enetaddr("ethaddr", enetaddr))
752 return;
753 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
754 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
755 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
756
757 for (i=0; i<0x40; i++) {
758 write_srom(dev, DE4X5_APROM, i, eeprom[i]);
759 }
760 }
761 #endif /* UPDATE_SROM */
762