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Searched refs:DUAL_DUNIT_CFG_REG (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_centralization.c84 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
88 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_centralization()
482 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_centralization()
520 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_special_rx()
525 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_special_rx()
Dddr3_training_leveling.c90 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, in ddr3_tip_dynamic_read_leveling()
95 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
320 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_read_leveling()
465 DUAL_DUNIT_CFG_REG, &cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
470 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
773 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
867 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_dynamic_write_leveling()
874 DUAL_DUNIT_CFG_REG, 0, (1 << 3))); in ddr3_tip_dynamic_write_leveling()
1169 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_write_leveling()
Dddr3_training_pbs.c61 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
66 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_pbs()
868 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_pbs()
Dddr3_training_ip_engine.c378 DUAL_DUNIT_CFG_REG, 1 << 3, 1 << 3)); in ddr3_tip_ip_training()
387 DUAL_DUNIT_CFG_REG, 0, 1 << 3)); in ddr3_tip_ip_training()
716 (dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_read_training_result()
860 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_load_all_pattern_to_mem()
Dmv_ddr_regs.h338 #define DUAL_DUNIT_CFG_REG 0x16d8 macro
Dmv_ddr_plat.c366 reg = reg_read(DUAL_DUNIT_CFG_REG); in ddr3_tip_a38x_select_ddr_controller()
373 reg_write(DUAL_DUNIT_CFG_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
Dddr3_training.c397 if_id, DUAL_DUNIT_CFG_REG, 0, in hws_ddr3_tip_init_controller()
1366 DUAL_DUNIT_CFG_REG, 0, 0x8)); in ddr3_tip_freq_set()
1640 DUAL_DUNIT_CFG_REG, in ddr3_tip_freq_set()
2713 if_id, DUAL_DUNIT_CFG_REG, 1 << 3, in ddr3_tip_enable_init_sequence()