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Searched refs:DW_OP_regx (Results 1 – 25 of 45) sorted by relevance

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/external/elfutils/backends/
Dia64_retval.c55 { .atom = DW_OP_regx, .number = 128 + 8 }, \
57 { .atom = DW_OP_regx, .number = 128 + 9 }, \
59 { .atom = DW_OP_regx, .number = 128 + 10 }, \
61 { .atom = DW_OP_regx, .number = 128 + 11 }, \
63 { .atom = DW_OP_regx, .number = 128 + 12 }, \
65 { .atom = DW_OP_regx, .number = 128 + 13 }, \
67 { .atom = DW_OP_regx, .number = 128 + 14 }, \
69 { .atom = DW_OP_regx, .number = 128 + 15 }, \
Dppc64_retval.c50 { .atom = DW_OP_regx, .number = 33 }, { .atom = DW_OP_piece, .number = 8 },
51 { .atom = DW_OP_regx, .number = 34 }, { .atom = DW_OP_piece, .number = 8 },
52 { .atom = DW_OP_regx, .number = 35 }, { .atom = DW_OP_piece, .number = 8 },
53 { .atom = DW_OP_regx, .number = 36 }, { .atom = DW_OP_piece, .number = 8 },
62 { .atom = DW_OP_regx, .number = 1124 + 2 }
Dsparc_retval.c52 { .atom = DW_OP_regx, .number = 32 }, { .atom = DW_OP_piece, .number = 4 },
53 { .atom = DW_OP_regx, .number = 33 }, { .atom = DW_OP_piece, .number = 4 },
54 { .atom = DW_OP_regx, .number = 34 }, { .atom = DW_OP_piece, .number = 4 },
55 { .atom = DW_OP_regx, .number = 35 }, { .atom = DW_OP_piece, .number = 4 },
Driscv_retval.c83 { .atom = DW_OP_regx, .number = 42 }, in pass_in_fpr_lp64f()
85 { .atom = DW_OP_regx, .number = 43 }, in pass_in_fpr_lp64f()
98 { .atom = DW_OP_regx, .number = 42 }, in pass_in_fpr_lp64d()
100 { .atom = DW_OP_regx, .number = 43 }, in pass_in_fpr_lp64d()
Daarch64_retval.c222 { .atom = DW_OP_regx, .number = 64 }, \ in pass_hfa()
224 { .atom = DW_OP_regx, .number = 65 }, \ in pass_hfa()
226 { .atom = DW_OP_regx, .number = 66 }, \ in pass_hfa()
228 { .atom = DW_OP_regx, .number = 67 }, \ in pass_hfa()
Dalpha_retval.c50 { .atom = DW_OP_regx, .number = 32 }, { .atom = DW_OP_piece, .number = 4 },
51 { .atom = DW_OP_regx, .number = 33 }, { .atom = DW_OP_piece, .number = 4 },
Dppc_retval.c59 { .atom = DW_OP_regx, .number = 33 }
66 { .atom = DW_OP_regx, .number = 1124 + 2 }
Dx86_64_retval.c52 { .atom = DW_OP_regx, .number = 33 },
54 { .atom = DW_OP_regx, .number = 34 },
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/ARM/
Dpartial-subreg.ll12 …[0x{{.*}}, 0x{{.*}}): DW_OP_regx D16, DW_OP_piece 0x8, DW_OP_regx D17, DW_OP_piece 0x4, DW_OP_regx…
Ds-super-register.ll7 ; CHECK: DW_OP_regx
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/Sparc/
Dsubreg.ll3 ; CHECK: [{{.*}}, {{.*}}): DW_OP_regx D0, DW_OP_piece 0x8, DW_OP_regx D1, DW_OP_piece 0x8
/external/swiftshader/third_party/llvm-7.0/llvm/lib/DebugInfo/DWARF/
DDWARFExpression.cpp79 Descriptions[DW_OP_regx] = Desc(Op::Dwarf2, Op::SizeLEB); in getDescriptions()
199 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx) in prettyPrintRegisterOp()
236 Opcode == DW_OP_bregx || Opcode == DW_OP_regx) in print()
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/ARM/
Dsplit-superreg-piece.mir6 …HECK-NEXT: [0x00000010, 0x00000018): DW_OP_piece 0x10, DW_OP_regx D0, DW_OP_piece 0x8, DW_OP_regx …
Dsplit-superreg.mir6 # CHECK-NEXT: [0x00000010, 0x00000018): DW_OP_regx D0, DW_OP_piece 0x8, DW_OP_regx D1, DW_OP_piece …
/external/llvm/test/CodeGen/ARM/
Ddebug-info-qreg.ll5 ;CHECK: sub-register DW_OP_regx
9 ;CHECK-NEXT: sub-register DW_OP_regx
Ddebug-info-sreg2.ll9 ; 0x90 DW_OP_regx of super-register
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Ddebug-info-qreg.ll5 ;CHECK: sub-register DW_OP_regx
10 ;CHECK-NEXT: sub-register DW_OP_regx
Ddebug-info-sreg2.ll10 ; CHECK-NEXT: [0x{{[0-9]*[a-f]*}}, 0x{{[0-9]*[a-f]*}}): DW_OP_regx D8
/external/elfutils/libdw/
Ddwarf_frame_register.c89 ops_mem[(*nops)++] = (Dwarf_Op) { .atom = DW_OP_regx, in dwarf_frame_register()
/external/libunwind_llvm/src/
Ddwarf2.h222 DW_OP_regx = 0x90, // ULEB128 register enumerator
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Ddebug-info-qreg.ll5 ;CHECK: DW_OP_regx for Q register: D1
10 ;CHECK-NEXT: DW_OP_regx for Q register: D2
Ddebug-info-sreg2.ll12 ;CHECK-NEXT: .byte 144 @ DW_OP_regx for S register
/external/llvm/test/DebugInfo/ARM/
Ds-super-register.ll7 ; 0x90 DW_OP_regx of super-register
/external/libunwind/src/dwarf/
DGexpr.c99 [DW_OP_regx] = OPND1 (ULEB128),
326 case DW_OP_regx: in dwarf_eval_expr()
/external/llvm/lib/CodeGen/AsmPrinter/
DDwarfExpression.cpp30 EmitOp(dwarf::DW_OP_regx, Comment); in AddReg()

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